Cadence Brings Timing to the Manufacturing Floor; Cadence Encounter Test Delivers True-Time Delay Test for Nanometer Design.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--May 18, 2004

Cadence Design Systems, Inc. (NYSE:CDN) today announced that it has brought timing to the manufacturing floor with True-Time delay test for processes at 130 nanometers and below. This addition to Cadence(R) Encounter(TM) Test helps ensure the highest Quality-of-Silicon (QoS) by detecting subtle IC defects. In conjunction with this announcement, Artisan Components has become one of the first design chain partners to announce True-Time certification of its 90-nanometer standard cell libraries.

True-Time detects subtle delay defects such as resistive opens that can cause catastrophic failures in the end-product application. With the addition of True-Time, Encounter Test is the first and only tool that uses actual standard delay format (SDF) timing information from the design process to create timing-accurate delay tests. By tightly controlling the timing of each test using True-Time, Encounter Test automatically maximizes the quality and effectiveness of the test for a given test coverage.

"We have worked very closely with Cadence as it developed True-Time," said Garry Hughes, vice president, ASIC development and worldwide design centers, IBM Systems & Technology Group. "With Encounter Test, we have been able to achieve transition fault coverage greater than 90 percent with automated calculation of tester timings. This is in addition to our existing 99 percent stuck-at fault coverage capability. We have seen shipped product quality improve by up to 2X. As a result, our goal is to use True-Time for all ASIC devices at 130 nanometers and below."

Encounter Test Design Edition uses True-Time delay test to detect the complex defects that become dominant in nanometer-scale designs. Encounter Test Manufacturing Edition provides world-class diagnostics for all detectable defects - including those discovered with True-Time. With a customer proven 80 percent callout accuracy, Manufacturing Edition accelerates the yield ramp goals of manufacturers.

As is the case with the IBM ASIC libraries, Artisan libraries have been certified for True-Time. With certified Artisan libraries, designers can be confident that all of the timing information required to generate True-Time delay tests is readily available and fully verified.

"As a leading semiconductor IP provider, Artisan believes that True-Time certified libraries can help designers reach silicon success," said Neal Carney, vice president of marketing at Artisan. "We believe that these libraries, when coupled with Encounter Test, will help provide an advantage to our customers."

"True-Time delay test provides Encounter Test customers the highest quality-of-test available in the industry," said Paul Estrada, general manager of Encounter Test for Cadence Design Systems. "We are delighted to continue the track record our development team has of delivering high-value test innovations."

True-Time is available immediately as part of the Encounter Test Design Edition ATPG Plus option.

About Cadence

Cadence is the largest supplier of electronic design technologies and engineering services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks and Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.