Cadence Announces Toshiba America Electronic Components Endorsement of Ambit BuildGates Static Timing Analysis in ASIC Design Flows.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 7, 2001

Cadence SP&R Design Tools Offer Unmatched Capacity and Performance for

Chip-Level Synthesis and Static Timing Analysis

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced that Toshiba America Electronic Components, Inc. (TAEC) has issued sign-off endorsement for the static timing analysis (STA) technology embedded within the Cadence(R) Ambit(R) BuildGates(R) synthesis and Physically Knowledgeable Synthesis tools for application specific integrated circuit (ASIC) design flows. Cadence integrates the STA capability with its full-chip, incremental common timing engine (CTE) across the entire Cadence SP&R (synthesis/place-and-route) product line. This gives users a unique sign-off quality design environment from RTL to GDSII. For designers working on chip-level synthesis and STA, the Ambit BuildGates synthesis and Physically Knowledgeable Synthesis (PKS) tools provide unparalleled capacity, performance, and sign-off quality results.

"TAEC has been performing static functional and timing verification for our multi-million gate ASIC designs in order to deliver fast design cycle times for our customers. We offer our customers a robust static timing sign-off methodology that has been proven in our deep sub-micron (DSM) production ASIC designs," said Jeff Berkman, senior vice president of SLI Engineering at TAEC. "We find that Ambit BuildGates' native STA capability, within Cadence's SP&R solutions, meets our static timing verification requirements. Ambit BuildGates is being integrated into our static timing verification tool suites and methodology, and will be an integral component in our DSM SP&R ASIC design flow."

By imbedding the STA capability fully into the entire SP&R front-to-back design flow, Cadence reduces constraint generation and verification time, enabling excellent timing correlation between synthesis and place-and-route. The integration of this static timing engine allows designers to easily and thoroughly identify and repair timing problems without leaving the design environment. The STA engine identifies critical timing paths, analyzes clock network skew, and checks set-up and hold-time requirements for a circuit. The inclusive Ambit BuildGates and PKS design architecture eliminates the need for a separate, standalone sign-off STA solution.

The Ambit BuildGates STA technology -- with its fast, yet comprehensive mathematical approach that eschews test vectors -- provides accurate timing analysis of multi-million gate designs. The tool's flexibility supports a wide variety of design styles, including multiple clocks (both edge-triggered and level-sensitive) with cycle stealing. The STA capability also enables fast, frequent, and thorough timing checks and incremental analysis across even the largest chips. In addition to its high capacity and performance, the integrated CTE technology enables concurrent optimization for timing and signal integrity issues, while still performing traditional STA tasks.

"By incorporating CTE into the full suite of SP&R tools, timing limitations have been greatly reduced, thereby enabling high-performance implementation," said Jeff Roane, vice president for SP&R marketing at Cadence. "Toshiba's endorsement of our STA solution further substantiates and confirms that we are providing the only synthesis tools in the industry with embedded sign-off quality timing analysis. Customers like Toshiba recognize that the integration of CTE with its STA capability in the SP&R product line provides them with more productive tools that are powerful, accurate, highly correlated, and sign-off quality. This provides a consistent design environment from RTL to GDSII."

About Cadence SP&R

Cadence SP&R consists of three products: Ambit BuildGates synthesis, PKS physical synthesis, and Silicon Ensemble(TM) PKS optimization place-and-route. This SP&R solution is superior to heterogeneous IC design environments, as it features correlation within three percent through common timing, synthesis, placement, and routing engines used by both logic designers and physical designers.

About Cadence PKS Physical Synthesis

Cadence PKS is the most complete and tightly integrated physical synthesis offering available today. It achieves tight correlation with final routed results because its synthesis, timing, placement, and true global routing engines are integrated into the same tool. This integration also provides better quality-of-results, seen in the frequency and area of the design.

About Ambit BuildGates

Ambit BuildGates synthesis enables customers to synthesize multi-million gate designs rapidly with superior results. Ambit BuildGates also has a built-in, high-capacity, high-performance timing analysis tool that enables productive timing closure. The distributed synthesis feature built into Ambit BuildGates leverages modern networked compute environments to dramatically reduce synthesis runtime for large designs.

Pricing and Availability

Static Timing Analysis is sold as part of the Ambit BuildGates and PKS synthesis solutions and not as a standalone tool. Ambit BuildGates and PKS synthesis products are available worldwide for UNIX-based workstations from Hewlett-Packard and Sun Microsystems, and for AIX-based workstations from IBM. One-year U.S. list prices start at $12,000 and $100,000, respectively. For information on international pricing, please contact a local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,400 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at www.cadence.com.

Note to Editors: Cadence, the Cadence logo, Ambit, and BuildGates are registered trademarks, and Silicon Ensemble is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.