Cadence Announces Design Solution for Extreme-Performance PCB Data Bus Architectures.

SAN JOSE, Calif.--(BUSINESS WIRE)--June 2, 1999--

SPECCTRAQuest Interconnect Designer Extended to Optimize Design

of New-Generation, Source-Synchronous Buses Critical to

PCB-Level Performance and Predictability of PCs

Today at the JPCA'99 show in Tokyo, Japan, Cadence Design Systems, Inc. (NYSE:CDN) announced a revolutionary solution for optimizing design of extreme-performance data bus architectures critical to the functionality of high-end personal computers (PCs).

This capability, which speeds the interconnect exploration and virtual-prototyping phase of printed-circuit board (PCB) design, is available in the latest version of SPECCTRAQuest(TM) interconnect designer, part of the Intrica(TM) family of PCB and integrated circuit (IC) packaging design products. To complement this leading-edge tool capability, Cadence offers a range of proven methodology services that focus on assisting in the rapid deployment of next-generation data bus-based PCs.

The new SPECCTRAQuest tool functionality targets rapid, accurate generation of data that takes into account all of the variables surrounding solution-space exploration, according to Dave DeMaria, vice president of marketing for PCB and IC packaging solutions at Cadence. "This area of the electronic systems market is growing incredibly quickly," said DeMaria. "Our view is that any vendor of high-end design tools that does not offer a viable source-synchronous bus exploration and design solution this year will not be able to offer customers in the high-end, high-speed market the capabilities that they need to compete."

The Performance Modeling Challenge

Most high-performance PCs utilize a new breed of bus architectures, such as Rambus, AGP 2 and 4x, or PCI-X, which enable data communication between emerging high-speed silicon devices without impeding chip or system performance. However, these new bus architectures necessitate a shift in both design methodology and design tool functionality because most current solutions are based on solving the 'common-clock' architecture used by previous data bus generations. These solutions are either inadequate or extensively time consuming when applied to new-generation bus architectures.

Additionally, many of the 'common-clock-focused' solutions use behavioral modeling and simulation techniques that merely approximate silicon performance. A major challenge facing emerging source-synchronous bus architectures is functional, accurate modeling of silicon performance. This will allow development of a bus-topology interconnect strategy that maximizes PCB-level system performance and predictability, whereas simple behavioral-modeling and simulation techniques can severely compromise chip and system performance.

The SPECCTRAQuest product's functional silicon macro-modeling capability enables the accurate modeling of all new silicon performance capabilities, without the need for compromise, and ensures maximum PCB-level silicon and system performance.

Defining and Optimizing Bus Implementation

Optimizing the interconnect-topology solution space is a primary goal of the data bus design engineer. Extreme-performance source-synchronous bus architectures, both with and without data pipelining (where the time between the data bits is shorter than the electrical length of the bus interconnect), require greater speed and data transfer than their predecessors -- in some cases, bus capacity can exceed 800 mega-transfers per second. While other high-speed design solutions are reflection-based and target the soon-to-be-obsolete common-clock architecture, the enhanced SPECCTRAQuest interconnect designer is aimed at meeting the demanding criteria of these advanced bus architectures.

Key features of the new PCB data bus architecture design capability include: -0-

--   Solution-space parametric sweeping, via an easy-to-use graphical
     environment, for rapid definition of the ideal design
     implementation using functional bus operational data thresholds;

--   Multiple-threshold device modeling and simulation support for
     accurate analysis of logic and buffer delay thresholds that vary
     with simulation condition;

--   Custom bus stimulus setup/editing for defining functional data
     protocols, bus speed, clock jitter and enable patterns in order
     to optimize performance, reliability and predictability of the
     bus implementation under real-world conditions; and

--   Custom simulation measurements with advanced waveform analysis
     capability that allows user-defined measurements of
     application-specific interconnect performance, such as
     timing-skew measurement between clock strobe and data signal at a
     source-synchronous device receiver.

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Adopting Next-Generation Bus Technology

Designing PCB motherboards with extreme-performance data buses can be a tremendous challenge for many systems companies, especially with competitive time-to-market and cost pressures added to tool adoption. To reduce the learning curve and risks of new technology adoption driven by relentless project schedules, Cadence Methodology Services provides specific knowledge and experience with advanced bus technology to ensure design goals are achieved. Available services include tool adoption and optimization, methodology implementation, and assisted pilot design projects.

The advanced device modeling, analysis and design capabilities of SPECCTRAQuest interconnect designer have already been proven with last year's introduction of the industry's first advanced design kit for the Intel Merced(TM) processor based on the IA-64 architecture.

Pricing and Availability

The data-bus-architecture upgrade to SPECCTRAQuest interconnect designer will be available in mid-September on Windows NT and Unix workstations, and is free to existing maintenance users. List price for the tool starts at US$9,995. Cadence Methodology Services are available immediately and are priced according to the specific requirements of each engagement.

About Cadence

Cadence Design Systems, Inc. is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.2 billion, Cadence is headquartered in San Jose, Calif., and has sales offices, design centers, and research facilities located around the world. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Note to Editors: Cadence and the Cadence logo are registered trademarks and Intrica and SPECCTRAQuest are trademarks of Cadence Design Systems, Inc. All others are properties of their holders.