CadMOS Design Technology Announces SeismIC, a Full Chip Substrate Noise Analyzer for Mixed-Signal ICs.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--March 16, 2000

Tool Performs Substrate Extraction and Noise Analysis,

Enables Safe Integration of Analog and Digital Components

CadMOS Design Technology, Inc. today announced SeismIC(TM), a substrate noise analyzer targeted at multi-million transistor mixed signal systems-on-chip (SOC) designs such as networking and wireless communications chips.

SeismIC(TM) enables ultra deep submicron (UDSM) designers to simulate and analyze the affects of substrate noise coupling throughout the design process and to catch noise induced failures prior to manufacturing.

"Substrate noise coupling has become a source of reduced performance in mixed signal, high speed networking ICs," said Augustine Kuo, analog design manager at Altima Communications. "We have successfully used SeismIC(TM) to simulate the affects of substrate noise coupling in our designs and have implemented several simple cost effective enhancements to improve the design robustness based on SeismIC(TM) results. With SeismIC(TM), we found potential noise problem areas and fixed them, avoiding costly silicon re-spins."

"SeismIC represents the second product in CadMOS' roadmap to provide SOC designers with solutions to the noise problems they face when using UDSM processes," said Charlie Huang, chief executive officer of CadMOS. "It addresses a key design problem that arises whenever sensitive analog components share a common substrate with increasingly noisy digital components."

Substrate Noise in Mixed Signal Systems

Mixed-signal design is characteristically plagued by substrate noise coupling between the high-speed digital and high precision analog circuits. When high-speed digital components switch, they inject currents into substrate, causing voltage fluctuations that can affect the operation of sensitive analog circuitry and cause them to malfunction. Furthermore, noise can also be injected into the substrate from supply rails via substrate contacts causing increased noise coupling to sensitive analog circuitry.

The substrate noise problem is particularly acute in high speed UDSM, SOC designs. As feature sizes decrease and design density increases, the distance between the noise sources and sensitive devices is dramatically reduced. Moreover, with higher clock frequencies, the digital circuits become noisier and consequently substrate noise interference is further aggravated resulting in an increased likelihood of noise failures that can seriously compromise system functionality, performance and production yields.

Traditionally, designers have relied on over-design and expensive processes to safeguard against substrate noise coupling in their designs. In many cases, particularly for high frequency UDSM designs, these approaches are insufficient, resulting in wasted silicon area and reduced operating performance.

About SeismIC(TM)

SeismIC(TM) is a breakthrough substrate noise analyzer that uses unique adaptive modeling techniques permitting accurate 3D-substrate extraction and noise analysis of multi-million transistor designs. SeismIC(TM) determines the major noise contributors and provides visual feedback by highlighting them on the layout.

SeismIC(TM) also has an option to provide advice on the design changes that will reduce the impact of substrate noise. For example, SeismIC can provide advice on the effectiveness of guard rings. Guard rings are typically used to reduce substrate coupling but overuse can mean wasted area and even an increase in the substrate noise observed by analog devices. SeismIC can advise when guard-rings should be inserted and when they should be removed.

With SeismIC(TM), designers can make cost-effective and educated design tradeoffs in selecting the best layout structure, process, package, and power supply distribution strategy that ensures substrate noise immunity in their designs.

Availability, Pricing and Interfaces

SeismIC(TM) is available now on SUN's Solaris 2.6. Pricing starts at $75,000 U.S. list for an annual time based license including maintenance. SeismIC(TM) integrates easily into existing design flows. It accepts a GDSII stream file and a layout extracted netlist in SPICE format. Other inputs include substrate process parameters, a signal toggle file from circuit simulation tools such as HSPICE, Spectre, StarSim or PowerMill and a package parasitic model including bond-wire and pin inductances.

SeismIC(TM) outputs waveforms and spectral components of substrate noise at sensitive analog components. The noise contributors and their contribution levels are highlighted using SeismIC's own layout viewer. When used with the design advisor option, SeismIC reports a list of recommended design changes to reduce substrate noise.

About CadMOS Design Technology, Inc.

CadMOS was founded in August 1997 by CAD and design experts from IBM and Synopsys/EPIC and is funded by U.S. Venture Partners, Intel Capital, Allegro Capital and private investors. The company is privately held, and is headquartered in San Jose, CA. CadMOS provides premium solutions and services to the electrical problems found in leading edge SOC designs.

CadMOS sells its products directly in the US and through distributors worldwide. CadMOS is located at 111 North Market, Suite 440, San Jose, CA 95113, USA. Telephone: [phone]. Fax: [phone]. Email: [e-mail]. Website: http://www.cadmos.com.

Note to Editors: Quote(s): Augustine Kuo 408/453-3700, Charlie Huang 408/795-1212.