COSSAP 7.0 Closes the "Gap" Between System Level Productivity and Efficient Silicon Implementation.

Inc. (NASDAQ: SNPS) today introduced Version 7.0 of its COSSAP digital signal processing design automation tool set with new capabilities that combine the productivity of system level design with the silicon efficiency of behavioral synthesis.

COSSAP's new features include: a graphical user interface (GUI), a Verilog co-simulation interface, and a library of behavioral hardware description language (HDL) models for digital filters. These features enable DSP designers to work at the system level while achieving the quality of results necessary for low cost, high performance systems.

"Our DSP design customers want to work at the highest possible level of abstraction to meet time-to-market requirements without compromising performance for their system design projects," said John Cooper, director of DSP marketing at Synopsys. "With COSSAP 7.0, we continue to evolve high-level design automation (HLDA) to raise system designer productivity.

"This methodology consolidates concept development and validation processes at the gate, register-transfer (RT) and system levels, and ensures the highest quality of results through implementation with the industry's leading logic synthesis tools."

New Entry, Simulation, and Modeling Capabilities

Synopsys has improved the entry environment of its high-level synthesis tools at the system-level by integrating the company's DesignSource design entry tool with COSSAP 7.0. This provides DSP designers with a new GUI and a host of entry and control features that ease design creation and modeling. Now, COSSAP 7.0 includes:

-- Improved image control and design checking in the block diagram editor.

-- The capability to quickly build and configure blocks according to their parameters, input/output data sets, implementations (C, behavioral HDL, RTL HDL), and scheduling conditions.

-- The capability to quickly target designs for simulation and automatic HDL code and DSP code generation from the block-diagram specification.

COSSAP 7.0 includes an interface with Verilog-XL to support co-design and co-simulation of hardware to shorten the turnaround time between specification and verification. Similar to support for existing VHDL co-simulation, Verilog co-simulation allows system designers to accept Verilog HDL code from hardware architects to perform full functional testing and debugging in a system context. With co-simulation, hardware architects can use COSSAP to develop "golden" executable system specifications for use as testbenches in the course of their Verilog development.

In addition to its new user and Verilog co-simulation interfaces, COSSAP 7.0 incorporates a library of behavioral HDL models for digital filters such as canonical finite and infinite impulse responses (FIRs and IIRs). Behavioral HDL models of these computationally-intensive filter operations are critical for efficient implementation.

With COSSAP, designers can explore various architectural alternatives through Synopsys' Behavioral Compiler using constraints to control area, circuit speed, latency, resource sharing, and scheduling. Together with Synopsys' Design Compiler logic synthesis tool, COSSAP and Behavioral Compiler form a complete path for system design, spanning algorithm, architecture, and implementation.

"After evaluating the Synopsys DSP design solution against those of other vendors, we found that Synopsys excelled in ease-of-use, tight integration with high-level synthesis, and quality of results," said Mike Paff, system design manager at Hyundai Electronics. "We are now completing a major design that combines HDL generated from COSSAP with hand-written code. It required less time to synthesize and verify the automatically generated logic from COSSAP than the manually generated logic.

"COSSAP allows the designer to produce the block diagram source which drives the entire design flow, thus ensuring that the final product performs exactly the same as the high-level simulations. Looking to the future, the features in COSSAP 7.0 will give us valuable benefits in system-level verification and architectural exploration."

Hardware/Software Co-Design and Co-Simulation

For DSP designers working in telecommunications applications, Synopsys now offers a Developer Kit for DSP Group's OAK core. The new Developer Kit includes an instruction-level simulation model which supports the COSSAP co-simulation capability for testing and verification of OAK-core-based designs. Synopsys leads the industry in its support for DSP processor models, which now covers all the major fixed-point DSPs from AT&T, Texas Instruments and DSP Group.

Pricing and Availability

COSSAP Version 7.0 is available in January 1996. Pricing starts at $40,000 U.S. list. A comprehensive COSSAP hardware implementation package is priced at $66,100 U.S. list. COSSAP 6.8 customers on software maintenance will receive upgrades to version 7.0 at no charge. The DSP Developer Kit for DSP Group's OAK core is available in January, priced at $7,500 U.S. list.

Synopsys, Inc. (NASDAQ:SNPS) develops, markets and supports high-level design automation models and software for designers of integrated circuits (ICs) and electronic systems. The company pioneered the commercial development of synthesis technology, which serves as the foundation of the company's high-level design methodology. Synopsys offers a comprehensive set of synthesis, simulation, test, and design reuse solutions, which support both Verilog HDL and VHDL. -0-

Note to Editors: Synopsys is a registered trademark of Synopsys Inc. COSSAP, Stream Driven Simulator, DesignSource, Behavioral Compiler and Design Compiler are trademarks of Synopsys Inc. Verilog-XL is a registered trademark of Cadence. Verilog is a registered trademark of OVI.

CONTACT: Synopsys, Inc.

Lisa Washington, 415/694-1853

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Scott Seiden, 415/637-8212