COMPASS to create integrated synthesis and floorplanning design flow with Synopsys tools; includes current product offerings and development of new products aimed at submicron design.

SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 12, 1994--COMPASS Design Automation, Inc. today announced that it is working with Synopsys, Inc. to provide solutions for deep submicron design. Specifically, COMPASS' floorplanning, placement and routing products and Synopsys' synthesis products will be more tightly integrated to create a complete and automated design solution optimized for designs of 0.6 micron and below.

"We currently have a solid design flow between Synopsys' synthesis tool and COMPASS' floorplanning tool and have seen tremendous success with hundreds of customer designs," said Steve Kompolt, product marketing manager at COMPASS. "As leaders in our respective fields, this link has been critical for today's deep submicron designs. Looking forward, we believe a tightly integrated design flow between Synopsys and COMPASS will be beneficial as our customers continue to move to finer process geometries."

Targeting emerging deep submicron designs, the new interface technology developed by COMPASS will support parasitics, PDEF and SDF and is expected to be available in the second quarter 1995.

"Synopsys is pleased to have COMPASS' support for Floorplan Manager," said Nitin Deo, product line manager for links to layout at Synopsys. "We will work with COMPASS to validate the interface to our synthesis tools. ChipPlanner software customers can now have tighter links with Synopsys synthesis tools to improve accuracy and time to market for deep submicron devices."

As the most widely supported ASIC vendor-independent floorplanner available today, COMPASS' ChipPlanner tool is currently supported by Toshiba, VLSI Technology, Mitsubishi, Hitachi, Hyundai, Goldstar, TSMC, American Microsystems, Inc. (AMI) and MHS, added Kompolt. The ChipPlanner tool is a vendor-independent floorplanner that provides placement capabilities and timing analysis, as well as a link between synthesis and layout.

New ChipPlanner Enhancements

Supporting the need for highly accurate placement capabilities for submicron designs, COMPASS also announced new enhancements to its ChipPlanner tool. Now, for the first time, customers have access to timing driven, path oriented placement embedded in a floorplanning tool. The new placement algorithms adhere to the path throughout the placement phase, including estimated and final placement, and meet timing constraints set forth by Synopsys' Design Compiler software. Additionally, the ChipPlanner tool is now the only floorplanner available that can optimize a design's clock tree during floorplanning and as part of the logic synthesis loop, reducing clock skew in the design. These enhancements yield dramatic improvements in density and convergence, higher predictability and less iterations for submicron design.

These new enhancements have also strengthened the current design flow between Synopsys and COMPASS. Today, users can synthesize designs using Synopsys' Design Compiler and then output the data in an EDIF file to COMPASS' ChipPlanner tool. ChipPlanner then automatically generates a floorplan and can accurately model the interconnect delay between circuit elements at each stage of design iteration. Customers can eliminate all timing violations using Synopsys' In-Place Optimization capabilities and COMPASS' sophisticated engineering change order (ECO) capability to update the floorplan. The ChipPlanner tool can then pass the optimized design to routers supporting the LEF and DEF format, with exact correlation to the floorplanned design.

Synopsys' Floorplan Manager software is a critical path optimization tool designed to take floorplanning information from external floorplanning tools and re-optimize the floorplanned designs to meet timing and design rule objectives. Synopsys is committed to providing its customers with complete solutions, which include strong technologies such as synthesis to layout links. Floorplan Manager is one such link between synthesis and external floorplanners.

COMPASS Design Automation is a leading provider of electronic design automation (EDA) tools and libraries for designing deep submicron application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs). The company supplies a complete set of tools for silicon implementation as well as front-end design and provides Foundry Flexible ASIC libraries, memory and datapath compilers, and library development tools. COMPASS is headquartered in San Jose, California, and develops, markets and sells its products worldwide. -0-

NOTE TO EDITORS: ChipPlanner and Foundry Flexible are trademarks of COMPASS Design Automation, Inc. Design Compiler is a trademark of Synopsys.

CONTACT: COMPASS

              Jeff Lewis, 408/434-7909
              Synopsys
              Lisa Young, 415/694-1853
              Tsantes & Associates
              Diane Orr, 408/452-8700
              VitalCom
              Scott Seiden, 415/637-8212