CLK Design Automation Links Verific Hardware Component Software to New Amber Timing Analysis Solution.Blazing Fast Verific Tool Handles Any Size Netlist, a CLK CLK Clock CLK Clerk CLK CDC2-Like Kinase CLK Corel RAVE (file extension) CLK Chep Lap Kok (Hong Kong airport) CLK Ceska Lekarska Komora (Chech) Design Automation Must ALAMEDA, Calif. -- CLK Design Automation today announced that has linked its Amber[TM] Analyzer, the industry's first true threaded and incremental static timing and signal integrity (SI) analysis solution, to Verific Design Automation's Hardware Description Language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) Component Software. Verific's Verilog Netlist Parser A routine that analyzes a continuous flow of text-based input and breaks it into its constituent parts. See parse. (language) parser - An algorithm or program to determine the syntactic structure of a sentence or string of symbols in some language. , a netlist-only parser that bypasses the HDL's parse-tree, is blazingly fast and handles any size netlist, a requirement specified by CLK Design Automation. It serves as the front-end to the Amber Analyzer and runs smoothly on 64-bit machines, another CLK Design Automation condition. Amber Analyzer is the first static timing and signal integrity tool that is fully threaded -- from reading designs, calculating delay and crosstalk, to generating reports. The Amber platform is fully incremental across all classes of analysis (timing, signal integrity, leakage) for any type of design change, such as cells swaps, netlist modifications, constraints, or parasitics. "With next-generation tools such as Amber, only the best-in-class software like those from Verific will help us meet complex design challenges," remarks Isadore Katz, president and chief executive officer of CLK Design Automation. "We found that the Verific HDL Component Software had the capacity and performance our customers require for their designs." Adds Michiel Ligthart, Verific's chief operating officer Chief Operating Officer (COO) The officer of a firm responsible for day-to-day management, usually the president or an executive vice-president. : "CLK Design Automation is helping to make multi-core processing design a reality. It gives us great pleasure to be working with team that is giving new meaning to timing analysis." Verific demonstrates its HDL Component Software in Booth #3464 this week at the 44th Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ) at the San Diego Convention Center The San Diego Convention Center is the main convention center for the city of San Diego, California. It is located in the Marina district of downtown San Diego near the Gaslamp Quarter, at 111 West Harbor Drive. in San Diego, Calif. To schedule a demonstration, visit Verific's website located at: http://www.verific.com. Or, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at rick@verific.com. CLK Design Automation debuts the Amber Analyzer at DAC. Attendees can see the Amber product overview in Booth #5671 or email sales@clkda.com to pre-arrange for a private demonstration. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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