CAST RELEASES JPEG CORES; FAST, COMPACT ENCODER AND DECODER READY FOR IMAGE PROCESSING APPLICATIONS.Semiconductor intellectual property (IP) provider CAST, Inc. recently announced the release of encoder and decoder cores for the popular JPEG JPEG in full Joint Photographic Experts Group Standard computer file format for storing graphic images in a compressed form for general use. JPEG images are compressed using a mathematical algorithm. image compression standard. These cores are designed to provide high-speed, space-efficient ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. or FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. JPEG implementations for digital cameras, video conferencing systems, scanners, surveillance systems, and portable display devices. Their speed and simplicity makes them especially suitable for cost-effective motion JPEG applications, such as inexpensive consumer-oriented digital camcorders. The cores offer baseline compliance with the ISO/IEC ISO/IEC International Organization for Standardization/International Electrotechnical Commission (ITU-T M 3000) 10918-1 JPEG standard. They support all the defined JPEG data formats and possible scan configurations, handle any image size up to 64k x 64k, and feature four stream-defined Huffman and Quantization (1) The division of a range of values into a single number, code or classification. For example, class A is 0 to 999, class B is 1000 to 9999 and class C is 10000 and above. (2) In analog to digital conversion, the assignment of a number to the amplitude of a wave. tables. The designs are programmable, fully-synchronous, and provide complete stand-alone operation with minimum memory requirements. Significantly faster than many competing products, the new JPEG cores are expected to achieve over 70 Mega samples/second for fast FPGA families, and even higher rates for ASICs. The cores are also space-efficient: just 3700 slices were used in the slower Xilinx Virtex-6 FPGA, with a speed of 55 Mega samples/second. Licensed from graphics processing expert and CAST development partner Alma Technologies S.A. (www.alma-tech.com), the new JPEG-Fast-E encoder and JPEG-Fast-D decoder cores are available now, in HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. form for ASIC synthesis or optimized for Altera or Xilinx devices. Pricing varies; contact CAST or your local distributor for details. The JPEG cores join CAST's general purpose IP (gpIP) line of cores, which also includes 8- and 16-bit processors, peripherals, buses, network interfaces, communications devices, and encryption functions. |
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