CAST Expands Memory Controller Line with IP Core for DDR2 SDRAM Devices.SANTA CLARA, Calif. -- Semiconductor intellectual property (IP) provider CAST, Inc. today announced a new IP core that implements a controller for all industry-standard DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM. DDR - Double Data Rate Random Access Memory and DDR2 memory devices. The new DDR2-SDRAM-CTRL IP core handles the interaction between SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. chips or DIMMs and the processor or a DMA (1) (Digital Media Adapter) See digital media hub. (2) (Document Management Alliance) A specification that provides a common interface for accessing and searching document databases. in a system using that memory. The core significantly simplifies memory management challenges for the developer, implementing all the necessary data management, initialization in·i·tial·ize tr.v. in·i·tial·ized, in·i·tial·iz·ing, in·i·tial·iz·es Computer Science 1. To set (a starting value of a variable). 2. To prepare (a computer or a printer) for use; boot. 3. , and address, and burst handling operations. A high-performance, pipelined and parallel architecture featuring a three-stage processing queue is designed to always get the most out of available system bandwidth. A clever core architecture splits the system interface into separate control, write-data, and read-data paths for easier integration and faster operation. Flexibility is ensured by making all memory parameters runtime-configurable, including timing, memory size, mobile-SDR support, and auto-refresh policies. Power-saving features include power down and self-refresh modes. Integration of the core is made easier for developers by delivering it with everything needed to for immediate use: one of two different PHY See physical layer and physical. physical device layers and data path queuing elements (FIFOs). The core itself is available in HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. source code, or as an optimized netlist for FPGAs and structured ASICs. Initial implementations of the core show it to be competitive in performance and area. For example, it achieved 262 MHz with under 1500 LUs in an Altera Sratix II, and 266 MHz with under 1300 slices in a Xilinx Virtex-4. These figures include the FIFOs and other elements not typically offered within a DDR controller core. The new core was developed by CAST partner Alma Technologies, based in Greece (see www.alma-tech.com). It joins the other cores in CAST's memory controller line: SDR-SDRAM-CTRL for single data rate mobile SDRAM devices, and NFlashCtrl ofor NAND flash memory devices. About CAST, Inc. CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City New York City: see New York, city. New York City City (pop., 2000: 8,008,278), southeastern New York, at the mouth of the Hudson River. The largest city in the U.S. , partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia. |
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