CAE Plus Introduces Open Simulation Environment for Virtual Prototyping of Embedded System ICs.SAN JOSE, Calif.--(BUSINESS WIRE)---Oct. 1, 1997-- ASVP ASVP Ada Simulator Validation Program ASVP Advanced Strategic Value Propositions (management consulting) ASVP Australian Society for Veterinary Pathology ASVP Air Saturated Vapor Pressure ASVP Area Senior Vice President Lab enables integration of existing hardware/software debugging tools and HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. and C models to verify embedded system IC software, hardware and systems performance CAE (1) (Computer-Aided Engineering) Software that analyzes designs which have been created in the computer or that have been created elsewhere and entered into the computer. Plus, Inc. (Austin, Texas), a supplier of high-level design (HLD HLD Hold (baseball relief pitcher statistic) HLD Homeland Defense (US) HLD High Level Design HLD High-Level Dialogue HLD High-Level Disinfection HLD Hyperlipidemia ) tools, core models, and services for the verification of embedded system integrated circuits (ICs), announced today that it is introducing an open application-specific virtual prototyping environment, ASVP Lab. ASVP Lab is used for verifying embedded system IC architecture, hardware and software. ASVP Lab offers embedded systems and software designers the opportunity to increase productivity and improve time-to-market while protecting their existing investment in design tools and models. For the first time, architecture, hardware and software can be debugged with clock accuracy together; and a product's performance measured against specifications before committing to logic design. Prototyping and verification of multi-processor system ICs is now feasible with ASVP Lab. According to Prem Jain, CAE Plus founder and president, "ASVP Lab is a breakthrough for verifying embedded systems. Now for the first time, architecture, software and hardware can be debugged and performance verified using real-time metrics." Jain added, "We have tested and developed ASVP Lab with several of our partners. It eliminated the ad hoc For this purpose. Meaning "to this" in Latin, it refers to dealing with special situations as they occur rather than functions that are repeated on a regular basis. See ad hoc query and ad hoc mode. methodology that was in place for embedded system hardware and software co-verification. Because it is open, ASVP Lab gives users the ability to continue to use legacy tools and models. Its clock accuracy gives the systems designers confidence in the system's performance and functionality early in the design cycle." (See related release today.) About CAE Plus' ASVP Lab CAE Plus' ASVP Lab includes a model assembler for RTL-C models, interfaces to Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. models, interfaces to hardware and software debugging tools from Design Acceleration (DAI) and Green Hills Software (GHS GHS Globally Harmonized System (of Classification and Labeling of Chemicals) GHS Greenwich High School (Connecticut) GHS Green Hills Software, Inc. ), and an Application Programming Interface (API) to integrate existing verification software. CAE Plus' ArchGen model development environment is used to develop RTL-C models. RTL-C models are executable specifications of embedded system IC cores. These cores (or models) are used to validate an embedded system IC's performance at speeds of 5,000 cycles per second (CPS). Models captured using ArchGen also generate consistent, logic synthesis-ready RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; models in Verilog or VHDL. ASVP Lab fills the verification needs of embedded system and software designers developing consumer products for telecommunication, multimedia, and networking applications. Pricing and Availability ASVP Lab pricing begins at $25,000 (US) for Windows 95, NT and UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). versions. It ships in December. Several validated microprocessor core models are available. The ArchGen environment is shipping now for Windows 95, NT, and UNIX. Prices begin at $60,000 (US). About CAE Plus CAE Plus is a supplier of high-level design (HLD) tools and services for specification and verification of embedded system ICs. The company offers: ArchGen, a model development environment; interfaces to hardware and software debugging tools; RTL-C models for microprocessors and related hardware; and design services. The company's offerings improve the performance, quality and reduce the cost of embedded system ICs. CAE Plus, Inc. is located at 9130 Jollyville Rd., No.340, Austin, TX 78759, 512/338-0165, Fax: 512/338-0192, comm@cae-plus.com, http://www.cae-plus.com -0- Note to Editors: ArchGen, ASVP Lab, and the CAE Plus logo are trademarks of CAE Plus, Inc. All other trademarks are the properties of their respective owners. Graphics are available on request. ASVP Lab design flow. Acronyms: API: Application Programming Interface ASVP: Application-Specific Virtual Prototype CPS: Cycles per second HDL: Hardware Description Language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. HLD: High-Level Design IC: Integrated Circuit RTL: Register Transfer-Level VHDL: VHSIC (Very High Speed Integrated Circuit) Pronounced "viz-ick." Ultra-high-speed chips employing LSI and VLSI technologies. The term comes from the name of the program launched by the U.S. Department of Defense in 1980 to advance digital IC technology. (Very High-Speed IC) HDL CONTACT: CAE Plus Public Relations public relations, activities and policies used to create public interest in a person, idea, product, institution, or business establishment. By its nature, public relations is devoted to serving particular interests by presenting them to the public in the most Counsel Georgia Marszalek, 650/345-7477 georgia@valleypr.com or CAE Plus, Inc. (Reader Inquiry Contact) Sandhya Shardanand, 512/338-0165 ext. 108 comm@cae-plus.com http://www.cae-plus.com |
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