CAE Plus Introduces New Versions of Its Pro-Active Virtual Prototyping Solutions for Embedded System IC Hardware/Software Development.

AUSTIN, Texas.--(BUSINESS WIRE)--May 11, 1998--

Upgrades Answer Customers' Requests for Increased Productivity;

ARCHGEN(TM) adds ISS model generation and VERILOG to 'C'

Conversion, AVSP LAB(TM) Allows users to select ISS or RTL-C

Models for Faster Verification Runs

CAE Plus, Inc., an Electronic Design Automation (EDA) supplier of virtual prototyping solutions, announced today that it is introducing new versions of its Pro-Active(TM) family of products-ArchGen 2.0 and ASVP Lab 1.1. The ArchGen model development environment and ASVP Lab virtual prototyping tool are used for embedded system-on-a-chip (SoC) integrated circuit (IC) design.

The improvements to CAE Plus' virtual prototyping solutions are in answer to customers' requests to improve productivity for hardware/software embedded system IC prototype development and verification. The new products will be demonstrated for the first time at the 35th annual Design Automation Conference, June 15-19 in San Francisco.

Prem Jain, CAE Plus founder and CEO, commented, "Historically, the introduction of hardware description languages and logic synthesis tools produced an order of magnitude increase in design productivity by moving IC design capture to the Register Transfer Level (RTL) and ensured a smooth automated path to gate-level design. Our ArchGen modeling environment enables a corresponding transition to the next level of design productivity by moving design capture to the behavioral level and providing a synthesis path to RTL models.

"The RTL-accurate models in 'C' satisfy IC designers' need for a fast simulating virtual prototype, for software development and hardware/software verification. Consistent HDL models satisfy the need for inputs to commercial logic synthesis tools."

Jain added, "As both the hardware and software content of embedded system ICs becomes increasingly complex, time-to-market requirements are creating a compelling need to capture designs at the behavioral level. ArchGen now provides true single source entry at the behavioral level and synthesis of RTL models in all of the formats required for software/hardware verification and logic design."

What's New:

CAE Plus' ArchGena behavioral modeling environment adds two important new features that significantly increase the user's productivity:

-- Automatic generation of Instruction Set Simulator (ISS)

models from the same source as RTL-accurate 'C' (RTL-C)

models, synthesizable RTL models in Verilog or VHDL and test

benches, ensuring the consistency of all model types and the

test bench.

-- A Verilog to 'C' conversion function enabling the capture of

datapath behavior in synthesizable Verilog supporting

current industry practice, then automatically converting

them to 'C' for 1000X enhanced simulation speed

ASVP Lab adds support for ISS models, complementing the new ArchGen ISS synthesis feature. Now an ISS processor model and the corresponding RTL-C processor model can both be integrated into an Application-Specific Virtual Prototype (ASVP) with the capability to switch between ISS mode and RTL-C mode at user-selectable points in the software.

The ISS model is functional, containing no detailed timing information, and executes 10 times faster than the RTL-C models or 10,000 times faster than typical HDL models. For example, an ISS model of the NEC V851 RISC processor executes at over 800,000 instructions per second on a Sun UltraSparc 2 workstation while the RTL-C model executes at about 80,000 cycles per second.

More ArchGen Improvements:

Just as important as the new features are the RTL optimization improvements implemented in ArchGen that result in both higher speed RTL-C simulation models and lower gate counts in the actual hardware. The ArchGen model synthesis algorithms have been optimized to yield a 40% average simulation speed improvement in RTL-C models and a 30% average gate count reduction in co-processor control logic synthesized from ArchGen HDL models, compared to version 1.4 of the tool.

Improvements have been made to the ArchGen GUI making it more flexible and intuitive for capturing the control and data flow of a design, and a new capability has been added for sharing ArchGen graphs and datapath components, enabling multi-user model development. The improvements to the GUI cut the time for specification capture in half without sacrificing model readability.

More About What's New:

Single-Source entry for RTL-C, ISS and HDL Models

The ArchGen environment provides the user with a Graphical User Interface (GUI) to capture the behavior of a core and automatically synthesizes RTL-level models of the core in several consistent formats. ArchGen adds an ISS model format to the existing RTL-C, and Verilog and VHDL models available today. While the overall functional behavior of the core has always been captured using the GUI, the datapath element's behavior has been coded by hand in 'C', then again in a HDL for logic synthesis, until now. The new Verilog to 'C' feature allows a datapath element's behavior to be captured in Verilog supporting current design practice, then consistent 'C' models of the datapath elements are generated for simulation in a virtual prototyping environment.

The new Verilog to 'C' capability improves model creation productivity dramatically, since the datapath elements are coded once instead of twice, the consistency of the models is assured requiring no checking, and Verilog is a more natural language for coding such elements than 'C'.

ISS/RTL-C Switching

The capability of automatically generating ISS processor models and switching between ISS processor models and RTL-C processor models in a simulation environment is an important new feature shared by ArchGen and ASVP Lab. After creation of the two types of models by the ArchGen tool, ASVP Lab is used to integrate them into an ASVP with the capability to switch between the models at user-selectable points in the software at run time. The RTL-C and ISS models share the same memory and registers so the state of the system is maintained when the processor models are switched.

Pricing and Availability:

ArchGen and 2.0 ASVP Lab version 1.1 will be released to customers in the third quarter of 1998. A minimum ArchGen configuration is priced at $80K, including RTL-C generation capability, and the ASVP Lab is $25K.

About CAE Plus:

CAE Plus supplies Pro-Active virtual prototyping solutions and services for the specification, development and verification of embedded system ICs. The ArchGen behavioral modeling environment enables single source entry for synthesizing RTL-accurate C models, fast Instruction Set Simulator (ISS) models and consistent HDL models. Both RTL-C and ISS processor models can be integrated into an ASVP.

The ASVP Lab tool, introduced last year, provides an open environment for constructing Application Specific Virtual Prototypes (ASVPs). ASVPs are stand-alone simulators of system ICs composed of RTL-accurate 'C', ISS and other C/C++ models, together with application software, application stimulus and interfaces to appropriate software debuggers and hardware analysis tools. ASVPs are used for early functional and performance verification of system ICs, and enable concurrent software/hardware development.

CAE Plus, Inc. is located at 9130 Jollyville Rd., No. 340, Austin, TX 78759, 512-338-0165, Fax: [phone], [e-mail], http://www.cae-plus.com. -0-

Note to Editors: The ArchGen, ASVP Lab and the CAE Plus logo are trademarks of CAE Plus, Inc. All other trademarks are the properties of their respective owners.

Graphics and Backgrounder on Design Productivity available on request.

Acronyms and definitions: ASVP: Application Specific Virtual Prototype C: popular programming language CAE: Computer Aided Engineering EDA: Electronic Design Automation GUI: Graphical User Interface HDL: Hardware Description Language IC: Integrated Circuit ISS: Instruction Set Simulator RTL: Register Transfer Level RTL-C: RTL-accurate 'C' SoC: System-on-a-Chip

CONTACT: Marszalek Public Relations Counsel

Georgia Marszalek, 650/345-7477

[e-mail]

www.cae-plus.com