C Level Design Validates Compatibility of System Compiler Synthesis Tool With Synopsys' Design Flows, Joins the Synopsys in-Sync Program.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Jan. 17, 2000 Interoperable Design Flow with Synopsys Key to Customer Success C Level Design, Inc. today announced that it has joined the Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ) in-Sync(R) program to enable interoperability of its system-level synthesis tool, System Compiler(TM), with the logic and datapath synthesis tools from Synopsys. C Level Design has validated System Compiler in design flows with both Design Compiler(TM) 9905 and Module Compiler(TM) from Synopsys. System Compiler automatically synthesizes ANSI C (language, standard) ANSI C - (American National Standards Institute C) A revision of C, adding function prototypes, structure passing, structure assignment and standardised library functions. ANSI X3.159-1989. cgram is a grammar for ANSI C, written in Scheme. source code into RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; and MCL MCL - Macintosh Common LISP netlists as required by Design Compiler and Module Compiler, providing a direct link from system-level design in C to RTL level synthesis. "Synopsys is the market leader in logic synthesis," said David Park, vice president of marketing at C Level Design. "The majority of our customers use Synopsys tools and it is important for them that our system-level synthesis tool feed directly into Design Compiler and Module Compiler without modification of the HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. code we generate." About Synopsys in-Sync Program Synopsys offers its partners the most extensive collection of interoperability programs and solutions available. In-Sync, as one such program, focuses on solving one of the designers biggest challenges today, EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tool interoperability. Leveraging industry standard and licensed formats, in-Sync works closely with its in-Sync members to jointly define, develop, verify and test optimal industry design flows which enable customers to spend more time designing and less time struggling with tool interoperability issues. For additional information on in-Sync and other Synopsys interoperability and licensing programs such as IP Catalyst and Tap-in visit Synopsys' web site at http://www.synopsys.com/partners. About C Level Design C Level Design, Inc. is a privately held company privately held company A firm whose shares are held within a relatively small circle of owners and are not traded publicly. founded in 1997 to develop and market system-level design automation software products for electrical engineers. C Level Design's tools dramatically reduce the time it takes to move from algorithm and system specification to hardware implementation. The company's products enable engineers to design and verify systems at the C level for higher performance and productivity, and then automatically compile their designs to HDL code that is compatible with industry standard synthesis tools from Synopsys, Cadence, and Mentor Graphics. For more information, visit: http://www.cleveldesign.com. Note to Editors: System Compiler is a trademark of C Level Design. Design Compiler, Module Compiler, Synopsys and in-Sync are trademarks of Synopsys. |
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