C Level Design Introduces C2Verilog Version 2.0 to Increase Productivity for Electronic System Designers.SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Dec. 14, 1998-- New System Level Synthesis Tool Provides Improved Results, Better Compilation Control, and Graphical User Interface graphical user interface (GUI) Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to C Level Design, Inc. today introduced C2Verilog(TM) version 2.0 with significant enhancements that increase design productivity for engineers creating complex electronic systems starting with the C language. C2Verilog version 2.0 includes new features that improve logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. results, provide greater control over the compilation process from C to Verilog hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) code, and make the tool easier to use in conjunction with other system-level design automation (SLDA), functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , and synthesis tools in the design flow. "We've focused our developments on improving design results with better compilation control and a better user interface," said Daniel Skilken, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of C Level Design. "Our customers find it easy to take the system specifications and algorithms that they have written in C and use C2Verilog to automatically compile them into HDL code for logic synthesis. The outstanding design results our customers are achieving, and the productivity gain they realize by eliminating the need to manually translate C into HDL code, validates the effectiveness of this new design methodology." C Level Design has made two enhancements in C2Verilog that dramatically improve logic synthesis results. Loop optimization In compiler theory, loop transformations play an important role in improving cache performance and effective use of parallel processing capabilities. Most execution time of a scientific program is spent on loops. , improves the compiler's handling of "FOR" and "DO-WHILE" loops in the C code. More efficient "FOR" and "DO-WHILE" loops dramatically impact the overall system performance. C2Verilog's loop optimization feature is transparent to designers and they can apply it to previously written C code without modification. To enable designers to replace portions of their generated HDL code with manually optimized IP blocks, for example register files, flash modules, and data paths, C2Verilog now supports hierarchy during compilation. Hierarchy support in the generated Verilog code also allows designers to perform logic synthesis on blocks in a piecewise fashion to accommodate the gate capacity limitations ofops that meet proper criteria to improve hardware implementation while maintaining C source compactness, maintainability, and readability. C2Verilog users can set a base memory address for all pointer calculations which simplifies C coding and increases control over hardware implementation at compile time The time it takes to translate a program from source language into machine language. Linker time may also be included in compile time. See compile and linker. (programming) compile time . The memory mapping Memory mapping is a process whereby some item of digital hardware is connected to a processor's address bus and data bus in such a way that it can be accessed (for reading and/or writing) exactly as if it were a memory cell. feature allows users to define variables as locations in memory, as registers in a register file or as (read only) values in a look-up table look-up table n (COMPUT) → tabla de consulta look-up table n (Comput) → table f à consulter look-up table n ( with transparency to C compilers and invocation only when compiling to Verilog. Designers of signal processing systems frequently define algorithms in C code using floating point arithmetic. Floating point arithmetic must be converted into fixed point arithmetic for hardware implementation in Verilog code. C2Verilog now compiles floating point number variables and operations into Verilog as fixed point variables and operations performing the proper arithmetic shifts necessary for multiplication. Automatic floating point conversion saves designers time manually rewriting their C code to use fixed point numbers. Finally, C2Verilog includes new syntax coloring and help features to improve the graphical user interface. Designers can now define and modify C2Verilog's code color schema to match the schema of other tools in their design flows. This capability helps designers understand code meaning, separate the actual code from comments, and locate syntax errors while eliminating confusion when they move between tools in the flow. In addition, C2Verilog's user help interface now supports hypertext navigation to simplify searching. Pricing and Availability C2Verilog version 2.0 is available immediately running on Unix and Windows(tm) computer platforms. Pricing starts at $75,000. About C Level Design C Level Design, Inc., (formerly CompiLogic Corporation) is a privately held company privately held company A firm whose shares are held within a relatively small circle of owners and are not traded publicly. founded in 1997 to develop and market system level design automation software products for electrical engineers. C Level Design's tools dramatically improve designer productivity from algorithm and system specification to hardware implementation. C Level Design's products generate HDL code that is compatible with industry standard synthesis tools from Synopsys and Cadence. For more information, visit www.cleveldesign.com. C2Verilog is a trademark of C Level Design. Windows is a trademark of Microsoft. |
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