Bug elimination tools to find million-dollar bugs in ASIC & IC designs; EDA startup zeros-in on tough bugs with two powerful new technologies.

Automation, Inc. today announced that it is tackling the problem of finding late-stage functional errors in HDL-based designs.

The startup is developing "assertion synthesis" and "directed search" technologies that will systematically search for tough bugs resulting from complex control interactions. The goal is to help design teams find tough bugs orders-of-magnitude faster than is possible using current verification techniques.

Advanced ASIC and IC design teams now spend over half of their time, effort, and resources on functional verification -- up to 80% of which goes into trying to find the last 20% of the bugs. Despite their efforts, many bugs go undetected, resulting in expensive silicon turns and field reliability issues.

The root problem is that running simulation, emulation, or even at-speed silicon for months exercises only a tiny fraction of the possible, but highly infrequent design behaviors. Current techniques just do not stress designs enough to find tough bugs prior to silicon.

0-In's assertion synthesis technology infers assertions from the design's original HDL specification, creating a checker module that quickly detects a wide range of bugs during simulation and directed search. Directed search is a hybrid of simulation and formal verification that efficiently exercises extremely difficult-to-test control interactions. Both technologies are industry firsts.

"Verification has become a nightmare because design teams do not have the right tools to find tough bugs," said Dr. L. Curtis Widdoes Jr., 0-In's CEO. "Simulation and emulation will continue to be critical technologies for getting designs to work correctly under typical operating conditions. However, they cannot stress-test designs massively enough to find the toughest bugs. Without innovations such as assertion synthesis and directed search, the inability to verify designs threatens to limit design complexity."

Conceptual Roots at Stanford University 

The conceptual basis for 0-In's technology has its roots in recent research on the FLASH multiprocessor at Stanford University. After extensive simulation of the FLASH HDL design, the design team measured the coverage of interactions between controllers in the design, and was surprised to find extremely low coverage.

Believing controller interactions to be a critical coverage metric, one researcher created a rudimentary tool that systematically exercised the interactions. The tool found every bug that was found using directed tests, plus a number of new, very difficult-to-find bugs.

The FLASH project taught two important lessons. First, coverage of interactions between pairs of controllers, known as "pair-arcs," is a critical metric for HDL design verification. Second, automated testing can find extremely tough bugs by systematically exercising pair arcs. However, the Stanford technique has limitations that make it impractical for commercial use; most notably it requires an independent cycle-accurate oracle.

Needing an alternative bug detection approach, 0-In followed up the Stanford research with a study of bugs in errata sheets, bugs that caused silicon turns, and bugs found late in the design cycle. The company identified a common signature for up to 50% of the toughest bugs. This signature, called a "register leak," is data loss or data corruption in a shared register or shared register file due to improper interactions between a pair of controllers.

Register leaks are caused by improperly specified control logic such as synchronization problems, "one-cycle-off" errors, or overlooked exception conditions.

Revolutionary Core Technologies

0-In is developing two core technologies for finding tough control-interaction bugs. The first new technology, directed search, efficiently exercises pair arcs. Preliminary data suggests that even the most extensive verification today exercises less than 10% of the pair arcs in complex designs.

High pair-arc coverage guarantees high coverage for lower-order metrics such as single-controller arcs and single-controller states. The second new technology, assertion synthesis, automatically creates HDL monitors that detect register leaks and a wide range of other bugs during normal simulation or directed search.

Directed search is the first practical hybrid of simulation and formal verification. The technology performs a prioritized, non-time-ordered expansion of simulation traces. Directed search uses formal verification techniques to enumerate and prioritize new behaviors and uses the design team's existing Verilog or VHDL simulator to exercise them. Since it interacts with the simulator once per cycle, directed search can readily take advantage of fast cycle-based simulators.

The technology provides orders-of-magnitude more efficient pair-arc coverage than current verification techniques. Thus, once a design functions correctly under typical operating conditions, directed search can perform a massive stress-test that zeros-in on tough control-interaction bugs.

Directed search provides the strengths of simulation and formal verification, without the weaknesses. While simulation can handle large designs and perform a wide range of checks, it provides very low coverage for infrequent behaviors. Model checking (a formal verification technique) provides exhaustive coverage, but only for moderately sized designs and a limited number of relatively straightforward properties. Directed search's hybrid approach provides high coverage for infrequent behaviors on large designs. Thus, it can find bugs that are typically not found until silicon testing today.

Assertion synthesis technology automatically creates an efficient checker module that detects register leaks and a wide range of other bugs near their sources. Assertions are one of the most powerful verification techniques, but they are vastly under-utilized because it takes too long to manually create each assertion. As a result, most design teams today rely primarily on end-to-end checks which check for high-level functional behavior at the design outputs.

Assertions complement end-to-end checks by providing two major advantages -- testbench independence and low detection latency. Testbench independence allows design teams to use the assertions in any simulation without any changes to the design or testbench. Low detection latency increases the probability of detecting a bug and makes debugging much easier.

Assertion synthesis brings the power of assertions to all HDL-based design teams. The technology quickly elaborates the design's HDL specification and identifies key structures such as controllers, counters, and shared resources. Based on a set of basic design rules, the technology then infers assertions and creates a checker module for use during simulation and directed search. Assertion synthesis is extremely fast, making assertions practical early in the design process.

An Evolutionary Methodology

0-In's bug elimination methodology is complementary to existing verification approaches. Design teams will continue to use their current verification methodologies to test their designs' basic functionality and known corner cases.

During this process, they can use assertion synthesis to create additional monitors that will catch register leaks and other problems which their testbenches exercise, but cannot detect. Once a design functions correctly under typical operating conditions, design teams will use directed search to massively stress-test the designs.

0-In is working with a number of leading-edge design teams and EDA vendors to ensure that the new technologies will fit into current design flows with little incremental effort. "We are working on revolutionary technology that we think will provide very high value," said Dr. Widdoes. "But, it is key to make this new technology fit into current design methodologies in an evolutionary fashion, so we are working closely with design teams as we develop a product."

Company Background

0-In Design Automation (pronounced "zero-in") provides products and services that help integrated circuit design teams quickly find functional errors in their designs. Founded in 1996, the company is privately held and based in San Jose.

0-In has an experienced management team which includes: Dr. Widdoes, CEO and chairman; Steven D. White, president; and Paul Estrada, vice president of marketing and applications. Dr. Widdoes is an EDA industry pioneer having co-founded Valid Logic Systems in 1981, received the coveted IEEE W. Wallace McDowell Award in 1984, and co-founded Logic Modeling Systems with White in 1987.

The company's technical team includes expertise in formal verification, simulation, coverage analysis, high-level synthesis, and ASIC design. 0-In has retained a distinguished technical advisory board comprised of experts from industry aONTACT: 0-In Design Automation

Paul Estrada, 408/487-3644

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