Brooktree Corp. introduces single-chip ATM SAR controller that directly supports per-connection traffic management for next-generation ATM.

SAN DIEGO--(BUSINESS WIRE)--March 13, 1995--Brooktree Corp. (NASDAQ:BTRE) Monday introduced a single-chip ATM Segmentation and Reassembly Controller (SRC) that is the first to offer an upgrade path to full compliance with key new ATM specifications being finalized during 1995.

The Bt8230 is based on a silicon architecture which implements a new per-connection management scheme. The new Available Bit Rate (ABR) Service being worked on by the ATM Forum needs this approach as opposed to current group management schemes. These new standards should lead to new mass deployment of ATM products.

The Bt8230 ATM SRC is sampling now and supports all requirements contained in the ATM Forum User Network Interface (UNI) 3.1 and related ANSI and International Telecommunications Union (ITU) standards. It can be used with Brooktree's Bt8222 Receiver/Transmitter Chip, introduced in January, to generate a complete, highly integrated and economical PCI ATM adapter solution.

The new Brooktree SRC is especially suited for ATM terminal adapters, routers/hubs and other WAN applications, which needs to support thousands of open connections simultaneously.

Key features of the Bt8230 include a proprietary transmit scheduling algorithm, which allows each connection to operate at an independent bit rate of up to 200 Mbit/s per channel. The scheduler generates standard compliant traffic. The device performs all AAL0, AAL3/4 and AAL5 SAR functions, supports 16,000 active Virtual Circuit Channels (VCCs) and includes a PCI host interface (master or slave mode).

Also, because ATM cells can be transferred directly into the main system CPU without local buffering, the Bt8230 architecture uniquely balances the strengths of the PCI bus with the need to achieve sustained 155.52 Mbps ATM speeds. This should result in lower cost ATM adapters since expensive dual port memory or local packet memory is not required.

Additionally, the Bt8230's new per-connection traffic-management architecture and other enhancements will allow it to implement new ATM specifications, chief of which is the new Class Y, Available Bit Rate (ABR) service, a new traffic-management definition developed by The ATM Forum so that ATM networks can emulate LANs.

ABR eliminates the previous ATM method of sharing bandwidth evenly among both active and inactive network connections, and replaces it with a more efficient method of dynamically allocating bandwidth between active connections, on-the-fly, to optimize performance networkwide.

A pin- and software-compatible update of the initial Bt8230 ATM SRC that fully implements the new ABR service and LAN-emulation standards will be sampling by Q3. It will be available as a drop-in replacement for the current Bt8230 SRC for customers who will have already initiated design work.

Other proposed ATM Forum interfaces and definitions should expand the attractiveness of ATM technology and therefore, increase the size of the ATM market. These include: -0-

o Private-Network Network Interface (P-NNI)--this new interface will enable the ATM campus-backbone switch market to support connections between switches so that large networks can be deployed. This interface also includes the new Class Y ABR service definition for emulating LAN traffic management.

o Broadband-Intercarrier Interface (B-ICI)--this new interface will allow service providers to transfer customer traffic, plus management and billing information, and market their services in a more meaningful way.

o Performance monitoring definitions--these definitions should significantly reduce the complexity of ATM network management and allow large networks to be managed by fewer people.

o Overall network management interfaces--these new interfaces will specify how information about the network will be communicated between different network elements.

To directly support these new specifications, the Bt8230 SRC architecture has several key differences as compared with previous architectures, primarily related to its provision for separate, real-time interaction between the ATM cell receive and transmit functions.

In particular, the Bt8230 includes necessary additional on-chip logic for direct, high-speed communication between the reassembly portion of the SRC and its segmentation scheduler. This is a critical capability for allowing the Bt8230 to individually manage connections, perform dynamic rate allocation and ATM to implement new performance-monitoring specifications.

The Bt8230 also includes on-chip logic for all necessary statistics-gathering for the more stringent ATM network management function.

"For high-speed, time-critical control requirements such as those imposed by the new ATM specifications, most control functions simply can't be handled in software -- they must be moved off the host processor and into specialized hardware," said Warner Andrews, product manager, Brooktree Communications Strategic Business Unit (SBU).

"Processor-based solutions for these next generation ATM systems will have severe difficulty keeping up with the new traffic- management and performance-monitoring requirements while still handling all of the other AAL processing duties at 155 Mbits/s and high numbers of active channels," Andrews added. "These new functions all have to be completed within a single cell time, or roughly 2800ns. This requires a silicon solution."

"The new Bt8230 ATM SRC represents significant progress for ATM. For example, when used with the processor wush as the i960(r) 32-bit RISC chip, the Bt8230 ATM SRC allows users to implement very high-performance ATM solutions, such as network interface cards, or high-speed switches," said Jim Kearns, strategic marketing manager, Intel's i960 Microprocessor Operation.

The new Bt8230 supports interleaved AAL5, AAL3/4,and SRC processing, which allows simultaneous support of ATM and SMDS. It also gives designers the option of a local processor to which signaling, Operations and Maintenance (OAM) tasks and ILMI management can all be ported. All signaling and ILMI can also be terminated into local memory to maintain management connections independent of the host.

Processor-less architectures are also easily supported, for applications like ATM network interfaces for file servers, routers/hubs, Digital Service Units (DSUs), WAN Data Terminal Equipment (DTE) and cost-effective PCI ATM cards. Designers can also opt for speed-selectable SRAM to further facilitate price/performance tradeoffs.

A choice of UTOPIA master, UTOPIA slave or Bt8222-compatible ATM PHY interface is available. The UTOPIA slave model allows the Bt8230 to be clocked by a switch fabric, which may be attractive to hub designers.

The Bt8230 is a single 33 MHz CMOS circuit packaged in a 208-pin Plastic Quad Flat Pack (PQFP) with direct TTL-level interfaces to the PCI bus. Samples will be available Q295 and volume production is scheduled for late Q395. The Bt8230 is priced $125 per unit in 100-unit volumes.

The Bt8230 will also be supported by a powerful, highly flexible ATM evaluation system that has been designed to provide significantly more resources and functionality than traditional ATM evaluation systems. The system is configured as a complete reference design with its own robust evaluation software, and will allow Brooktree's customers to substantially reduce their hardware and software design efforts, their R&D costs and time to market for Bt8230-based products.

For more information, contact Brooktree at 800/2BT-APPS, or contact the company via the Internet at apps(at-sign)brooktree.com.

Brooktree designs and markets high-performance digital and mixed-signal integrated circuits for computer graphics, multimedia and communications applications. The company, which has its headquarters in San Diego, employs more than 575 people worldwide. Revenues for the fiscal year ended Sept. 24, 1994, were $109 million.

CONTACT: Brooktree Corp., San Diego

Bill Berridge/Karen Paulovich, 619/535-3273 or -3516

or

The Benjamin Group Inc.

Carolyn Fromm or Marissa Jabczenski, 714/753-0755