Brion Releases Imaging Solutions to Support Advanced Memory and Logic Scaling.

SANTA CLARA, Calif. -- Brion Technologies, an ASML company, today announced it has added significant options to two key product lines, Tachyon OPC+ and LithoCruiser. Combined with the recent shipments of high NA immersion scanners, Tachyon OPC+ version 7.06 and LithoCruiser version 2.2 are enabling the next generation of device scaling.

Tachyon OPC+ now provides an optional full-chip implementation of ASML's patented Double Dipole Lithography (DDL). DDL enables semiconductor manufacturers to create smaller chip features by splitting dense circuit patterns into horizontal and vertical masks, then exposing them sequentially. DDL allows chip manufacturers to perform advanced 0.30 k1 imaging. Compared to two-etch double patterning, DDL lowers IC production costs and reduces cycle time by using only one etch step.

Additionally, Tachyon OPC+ supports a Model-based Scattering Bar Placement option that uses a patented Brion technique to ensure optimal placement of sub-resolution assist features. This model-based approach - calibrated to actual scanner and fab production results - reduces the time required to optimize a lithography solution, which results in getting new technology nodes to market sooner.

"The rapid implementation of DDL technology into Tachyon OPC+ demonstrates Brion's ability to quickly bring to market new computational lithography capabilities," said Neal Callan, Brion's vice president of product operations.

LithoCruiser 2.2, Brion's simulation software suite for analyzing and optimizing lithography processes, adds several new exclusive options, including Source-Mask Optimizer (SMO). LithoCruiser's SMO is the only commercial SMO package available that incorporates ASML scanner capabilities and model-based optical proximity correction (OPC) to improve the contrast and resolution of low-k1 repetitive chip features. Several major semiconductor makers are beginning to use SMO to enhance their advanced low-k1 lithography programs.

LithoCruiser also now features Batch Optimizer, a new software capability in the NA/sigma and OPC optimizer option. Batch Optimizer speeds customers' process development simulation flow by providing multi-step sequencing for complex optimizations, such as optimizing scanner settings to match critical dimensions through pitch of multiple scanners.

Keith Gronlund, Brion senior manager, product marketing, noted that LithoCruiser 2.2 complements Brion's other platforms. "The new additions to LithoCruiser 2.2 are specifically designed to further enhance the accurate representation and optimization of today's most advanced scanners for critical process development," he said.

These new Tachyon OPC+ and LithoCruiser options are available immediately.

About Double Dipole Lithography (DDL)

Double Dipole Lithography (DDL) is a patented ASML double-patterning technique that uses horizontally polarized light in one exposure, followed by vertically polarized light in another. DDL lowers IC production costs and reduces cycle time by allowing the use of one fewer etch step than most other double-patterning approaches.

About k1

Lithographers use the "process factor" k1 to express the relative difficulty of a given lithography process. Improvements in lithography system capabilities, photoresist processes, and masks enable lithography at smaller k1 values, which in turn allows chipmakers to produce devices with increasingly smaller features, with minimal sacrifice of process latitude.

About Source-Mask Optimizer (SMO)

Source-Mask Optimizer (SMO) is an ASML proprietary software option in LithoCruiser that simultaneously optimizes the ASML scanner illumination shape/settings and the model-based OPC for critical low k1 memory core features. SMO features include: full integration with access to LithoCruiser's on-board ASML scanner specification database, multi-clip optimization with weighting, overlapping process window and mask error enhancement factor (MEEF) as metrics.

About Brion Technologies

Brion Technologies is an ASML company and industry leader in computational lithography for integrated circuits. Brion's Tachyon[TM] platform, an OPC and OPC verification system, enables capabilities that address chip design, photomask making and wafer printing for semiconductor manufacturing. Brion is headquartered in Santa Clara, California. For more information: www.brion.com or www.ASML.com

(c) 2007 Brion Technologies Inc. All rights reserved. Brion Technologies, the Brion Technologies logo, and Tachyon are trademarks of Brion Technologies.