Breakthrough Technology in Tuxedo-LEC Enables Full Chip Functional Closure; Unique Capability Fuels Market Share Growth.

Business Editors and High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--April 17, 2000

Version 2.0 of Tuxedo-LEC, the highest performance equivalence checker on the market, includes major technological innovations that enable it to compare full chip, structurally dissimilar designs that have traditionally confounded all other tools and approaches, thereby providing complete functional closure from RTL to final netlist.

These innovations allow Verplex to reliably complete RTL-to-netlist functional comparisons of entire multi-million gate designs as a whole, even designs containing wide multipliers, hand-crafted memory, pipeline re-timing, state encoding changes, wide datapath, complex finite state machines, incomplete logic, custom transistor logic, and designs produced by the newest generation of physical design tools such as Magma Design Automation's Blast Fusion(TM). Without this unique Verplex capability, users may be forced into performing more verification iterations, one for every major design step that introduces significant structural change, or to break the design into smaller pieces, or to black box significant portions of it. An additional key feature of the latest Tuxedo-LEC version is a hierarchical module comparison manager, which was specifically created to enable users to quickly navigate and differentiate between functional bugs and benign hierarchy changes due to timing optimization. The latest Verplex release also adds full VHDL and EDIF capability, plus Linux support and ports to the latest 64 bit HP and Sun operating systems. Crediting the ability to achieve functional closure by completing larger and more complex RTL-netlist comparisons, Verplex has achieved phenomenal market share growth and now boasts of a diverse installed base at more than 80 customer sites including Cisco, Hewlett Packard, Lucent Technologies, NEC, Toshiba, Fujitsu, Mitsubishi, Texas Instruments, Alcatel, Agilent Technologies, Philips and Ericsson.

Functional closure is analogous to timing closure in that a successful RTL-to-netlist comparison ensures that an implementation fulfills its corresponding RTL specification requirement. Not only does functional closure assure that all of the design implementation steps are checked in a one step collective, it is particularly important for the reuse of intellectual property. It is essential that an RTL specification is functionally identical to its silicon counterpart in order to guarantee correct reuse of the RTL design.

Tuxedo-LEC is the first equivalence checker to offer full RTL-to-netlist support of wide multipliers, which are critical components of communications and digital signal processing systems. Utilizing proprietary algorithms and techniques, it easily handles comparisons of up to 64x64 bits using various architectures including carry-shift-add (CSA), Booth's algorithm, and Wallace Tree. During a recent customer benchmark, Tuxedo-LEC fully completed a 48x48 bit carry-shift-add (CSA) RTL-gate comparison in less than 10 minutes, whereas the nearest competitor was forced to abort when attempting to verify a 12x12-bit version of the same circuit.

RTL-to-netlist multiplier comparisons can pose a particular challenge to equivalence checkers because of the logical complexity of the multipliers themselves and the lack of structural similarity between the RTL and netlist descriptions. Due to the lack of structural similarity, it is more difficult to identify intermediate correspondence points that could be used to break the complex proof into smaller, more manageable proofs. Verplex R&D engineers have implemented innovative algorithms that enable Tuxedo-LEC to manage both the complexity and structural dissimilarity issues while maintaining high performance.

Tuxedo-LEC is also the first to add support for hand-crafted memories, which is another particularly difficult class of circuitry. Past conventional approaches chose to deal with each memory bit as a potential state bit, thus complexity of the proof rapidly grew too difficult even for relatively small memories. Alternatively, Verplex developed advanced techniques that are able to verify large hand-crafted memories quickly and easily.

With the latest release, Tuxedo-LEC offers unparalleled support of sequential pipeline re-timing and state encoding changes, which makes it the preferred tool for verifying designs that have been highly optimized in order to attain faster timing closure. Sequential pipeline re-timing moves combinatorial logic from one side of a latch or flip-flop to another in order to improve the speed. Due to this movement, hierarchical boundaries can become muddled and storage elements of the two designs become more difficult to correlate. State encoding changes can be made for multiple reasons, but are often done to reduce the amount of intermediate decoding logic and thus improve the speed. When changing from a binary to gray coding, the number of latches or flip-flops will increase and the intermediate logic will change, so again it becomes much more difficult for conventional equivalence checkers to correlate the designs.

As a leader in the newest generation of physical design systems, Magma Design Automation's Blast Fusion(TM) system creates a "correct-by-construction" circuit implementation without the need for timing closure iterations. "Tuxedo-LEC is the most capable equivalence checker we've seen for handling the high level of optimization needed for zero-iteration timing closure. We use Tuxedo-LEC regularly at our customer support centers worldwide. Through our cooperative work in Magma's MagmaTies(TM) interoperability program, our companies have demonstrated that Tuxedo-LEC and Blast Fusion enjoy a high degree of accuracy and correlation, and we recommend Tuxedo-LEC to our customers," stated Michael Battat, MagmaTies Program Manager at Magma Design Automation.

When hierarchical boundaries are flattened or modified due to optimization, it is difficult for the designer to envision these changes during equivalence checking. For this reason, Verplex has included a hierarchical module comparison manager with its latest Tuxedo-LEC release. The supplemental user interface displays a graphical representation of design hierarchy and enables the user to cross probe on correspondence points of each design being compared. The hierarchy manager was also developed in order to support the ASIC vendor or verification engineer specialist who may be relatively unfamiliar with the designs being verified. Additionally it is useful in visualizing the hierarchy of unfamiliar intellectual designs produced by third parties.

The 2.0 release also enables the user to specify general constraints, which are useful in minimizing false negatives when verifying designs with incomplete or missing blocks of logic. This often happens when designing systems at the block level, when integrating third party blocks of intellectual property, or when interfacing with external logic blocks. Without access to models for every block, an equivalence checker will rigorously check all combinations of possible boundary conditions. The tool may thus conclude there are some functional differences, even though some of them would be logically impossible had all of the boundary conditions of the missing logic been known. By supporting general constraints, the user can easily specify these boundary conditions and thus minimize the possibility of false negatives.

Wide datapath and complex finite state machine designs can sometimes be difficult for some equivalence checkers due to the high numbers of latches and flip-flops, which are usually represented as state bits. Basic enhancements to Tuxedo-LEC's proof engine have yielded additional capacity when handling these types of designs

Version 2.0 of Tuxedo-LEC also adds full VHDL support, including a variety of constructs such as multi-dimensional arrays and record types. The Verplex tool now offers support for both VHDL and Verilog languages, or designs containing a mixture of both, from RTL through gates and transistors. Furthermore, Tuxedo-LEC now offers EDIF netlist support.

Tuxedo-LEC version 2.0 also adds support for additional operating systems including the latest 64 bit HP and Sun operating systems, plus Linux. Tuxedo-LEC version 2.0 is available now at a single unit perpetual license price of $105,000.

About Verplex Systems, Inc.

Verplex Systems, Inc. is the only company that provides full chip functional closure from RTL specification through GDSII for multi-million gate designs. Verplex offers the highest speed, largest capacity, and easiest to use formal verification products in the industry for complex system-on-a-chip ICs. Verplex aggressively develops advanced algorithms and is the superior technology provider in the functional verification market. Verplex products target ASIC and IC engineers who demand formal verification tools which are both easy to use and reliable. For more information, visit www.verplex.com.

Note to Editors: Verplex and Tuxedo-LEC are trademarks of Verplex Systems, Inc. All other companies and products referenced herein are trademarks or registered trademarks of their respective holders.