Berkeley Design Automation's PLL Noise Analyzer(TM) Accelerates Time-To-Volume; Precision Circuit Analysis(TM) Technology Enables Japan's Leading DRAM Supplier To Deliver High-Speed Memory Devices On Time.

SANTA CLARA, Calif. -- Berkeley Design Automation Inc., a provider of innovative silicon analysis tools for analog/RF and mixed-signal applications, today announced the adoption and successful deployment of PLL Noise Analyzer. Elpida Memory, Inc. was able to meet the high-performance, low-noise, and low-power specifications for the phase-locked loops (PLLs) in their advanced memory chips by using the fast and accurate noise analysis and diagnostic capabilities provided by Berkeley Design's Precision Circuit Analysis(TM) technology.

"Elpida's advanced memory devices run at very high clock rates and must meet very tight noise specifications," said Yoshitaka Kinoshita, product development officer at Elpida. "The ability of PLL Noise Analyzer to provide fast and accurate transistor-level jitter analysis for the PLLs in our designs before tape-out enabled us to reduce the number of silicon prototype cycles and thereby accelerate our time to volume."

DRAM products must meet high performance and low power specifications, while also providing high capacity. With traditional analog/RF analysis methodologies and tools, there is a gap between what the designers observe in simulation compared to the actual silicon measurements - this is called the analysis gap. This gap makes it necessary to produce multiple silicon prototypes to accurately characterize these designs, resulting in delayed time to volume and increased product development costs.

Berkeley Design Automation has developed next generation circuit analysis technologies, called Precision Circuit Analysis (PCA), to close the analysis gap by allowing designers to accurately characterize their designs before tape-out. PLL Noise Analyzer, the company's first product, is the industry's only tool that accurately characterizes the noise and jitter performance of nonlinear circuits, such as PLLs and VCOs, at the transistor level. Berkeley Design's proprietary Stochastic Nonlinear Engine(TM), a key component of the PCA technology and the foundation of PLL Noise Analyzer, provides fast and accurate analysis of the nonlinear, time-varying behavior of full PLL circuits at the transistor level. By supporting standard HSPICE and Spectre netlist and model formats, PLL Noise Analyzer can be easily adopted into existing verification flows.

"We are excited that Elpida has chosen PLL Noise Analyzer to verify the noise performance of the PLLs in its most advanced memory devices," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "Our Precision Circuit Analysis technology provides incredible speed and accuracy that allows companies such as Elpida to reduce silicon re-spins and get their chips to volume production on time."

About Berkeley Design Automation

Berkeley Design Automation Inc. was founded in 2003 to address the verification challenges in the design of next-generation high-performance analog/RF integrated circuits (ICs). Berkeley Design Automation is a venture-backed, private company funded by Woodside Fund and Bessemer Venture Partners. The company's technology characterizes the nonlinear, time-varying behavior of complex analog and RF circuits, providing extremely accurate predictions that dramatically reduce the need for silicon re-spins. The company's first product, PLL Noise Analyzer, the industry's first noise analysis tool for phase-locked loops (PLLs), has already been adopted by semiconductor industry leaders. For more information, see http://www.berkeley-da.com.

PLL Noise Analyzer, Stochastic Nonlinear Engine, and Precision Circuit Analysis are trademarks of Berkeley Design Automation, Inc.

Berkeley Design is a registered trademark of Berkeley Design Automation, Inc.

HSPICE is a registered trademark of Synopsys Inc. (NASDAQ:SNPS). Spectre is a registered trademark of Cadence Design Systems Inc. (NASDAQ:CDNS).