Bay Microsystems Boosts Functional Verification With Tharas Systems' Next Generation Hammer Hardware Accelerator.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Oct. 15, 2002 Tharas Systems, Inc., a provider of high-performance, hardware-assisted design verification solutions, announced today that Bay Microsystems, Inc. has upgraded its verification flow with Tharas Systems' latest generation of Hammer hardware accelerator. "Last year, when we deployed Hammer hardware accelerator for Montego chip verification, it was an order of magnitude A change in quantity or volume as measured by the decimal point. For example, from tens to hundreds is one order of magnitude. Tens to thousands is two orders of magnitude; tens to millions is three orders of magnitude, etc. faster than the fastest HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. simulator. We deployed Hammer to successfully verify real network traffic, consisting of extremely long test sequences. We are now pleased to upgrade to the next generation 16 Million Gate capacity Hammer hardware accelerator for our current projects," said Tony Chiang, Sr. Vice President of Engineering at Bay Microsystems. "We are pleased that Bay has been able to leverage the power of Hammer hardware accelerator. Real traffic patterns cannot be sliced and fed to a Simulation Farm. It can take as much as two weeks to verify in software using the fastest workstation what Hammer simulates in mere hours. The only viable option for such long verification pattern is to deploy hardware acceleration In computing, hardware acceleration is the use of hardware to perform some function faster than is possible in software running on the normal (general purpose) CPU. Examples of hardware acceleration include blitting acceleration functionality in graphics processing units (GPUs) and . This significantly impacts functional verification of complex chips and systems," notes Prabhu Goel, Chairman and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. for Tharas Systems. Tharas Systems' Hammer provides a Verilog simulation platform that enables accelerated compile and run times while delivering ease of use and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. features comparable to that of software simulators. Hammer compiles 10 Million RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; gate-equivalent in as little as one hour vs. up to eight hours per Million RTL gate-equivalent for FPGA-based systems. Run times range from 10 to 1,000 times faster than the fastest software HDL simulators. Hammer's innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug -- a significant improvement over competing FPGA-based systems during debug. Hammer works with existing RTL and gate-level verification environments. As a result, designers can continue to use their verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ) and Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc. (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ). Hammer supports design sizes of up to 128 Million Gate-equivalent RTL code, and 16 Gigabyte in hardware. Hammer pricing ranges from US$115,000 to US$1,980,000. About Tharas Systems Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer(TM) offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/. For more specific product information, email info@tharas.com or call 1-408-855-3200. About Bay Microsystems Bay Microsystems, Inc. is a privately held, fabless communication IC company. Bay's Internetworking Processor(TM) (InP) Family of programmable packet processing devices combines scalability, intelligence processing and ultra-high performance in highly integrated solutions. The InP(TM) Family includes Montego(TM), the industry's first single-chip highly integrated OC192c/10G Network Processor, Traffic Manager and SAR (Segmentation And Reassembly) The protocol that converts data to cells for transmission over an ATM network. It is the lower part of the ATM Adaption Layer (AAL), which is responsible for the entire operation. See AAL. SAR - segmentation and reassembly . Bay's highly experienced management and world-class engineering team have three generations of proven expertise in architecture, implementation, deployment, marketing and management of packet processors. For more information visit the Web site at www.baymicrosystems.com. Note to Editors: Hammer(TM) is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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