BOPS Introduces Industry-leading, Low-power, High-performance DSP Cores for Mobile Wireless Markets.

Business Editors/High Tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 21, 2001

New DSP Cores Deliver Unprecedented 100 MIPS/mW;

Focus on High-Growth Markets for 2.5G and 3G Handsets and Mobile

Wireless LAN Devices

BOPS, Inc., the leading provider of programmable broadband digital signal processing (DSP) cores, today introduced families of cores designed to extend battery life without giving up the high performance required by the next-generation of mobile devices.

"The problem system designers of mobile broadband wireless devices have to deal with today is the trade-off required between power and performance: higher performance typically requires more power," explained Mark Bowles, president and COO, BOPS, Inc. "BOPS(R) newest cores solve this problem by delivering 100 MIPS/mW or more than five times the performance of existing low-power DSP chips. Ours is the disruptive technology needed to break the chokepoints that exist today in getting broadband data and high-quality video onto cell phones, PDAs (personal digital assistants) and handheld personal computers."

All BOPS low-power cores achieve an industry-leading 0.01mW/MIP (16-bit RISC equivalent MIPS). Performance of cores range from 1000 MIPS - 4000 MIPS and power consumption for cores, not including memories, range from 11mW - 36mW allowing customers to select cores with optimum balance of cost, performance, and power for their specific application.

The cores and their application power with memories include:

-- MoCARay, which delivers complete GPRS/EDGE baseband layer 1 processing at
less than 20mW and turbo codec processing at less than 50mW enabling
software-defined tri-mode 2G/2.5G/3G handsets.

-- MICoRay, which delivers full duplex MPEG4 CIF codec processing at less than
100mW enabling high-quality video conferencing on smartphones and PDA's.

-- WirelessRay, which delivers physical layer processing for 802.11b, 802.11g
and 802.11a at less than 70mW for wireless local area network (LAN) devices.

All low-power cores act as thread co-processors to ARM, MIPS, and other industry-standard low power CPUs. As thread co-processors, BOPS new cores are capable of handling multiple communications and imaging threads independent of the RISC CPU and thus provide superior power efficiency and performance headroom compared to single RISC implementations with DSP extensions. The new cores take advantage of BOPS ManArray(R) architecture's inherently low-power parallel architecture, low-power RTL design techniques, and SRAM design techniques.

"The BOPS ManArray architecture has always been known for its high performance and compute efficiency," said Will Strauss of Forward Concepts. "However, the high level of parallelism in the architecture has proved to provide unanticipated low-power benefits as well, making it well-suited for mobile wireless applications."

During the design process, BOPS used best-in-class design tools to minimize power consumption of its low-power cores. Synopsys' Power Compiler(TM) was used to deliver "push-button" power optimization, achieving 40 percent power reduction automatically.

Concurrently, BOPS also announced a Wireless LAN SOC in a Box(TM), a pre-packaged application solution that includes complete sample hardware and software along with implementation services for Orthogonal Frequency Division Multiplexing (OFDM)-based applications. (See press release "BOPS Announces Wireless LAN SOC in a Box," dated May 21, 2001.) The Wireless LAN SOC in a Box uses the WirelessRay core to create systems-on-chips for wireless LAN applications.

BOPS WirelessRay(TM), MoCARay(TM) and MICoRay(TM) cores are available as hard cores on 3Q01 and soft cores today. Synthesis and physical design was performed using industry-standard tools and target TSMC's 0.13i process. Data sheets on the cores are available at http://www.bops.com. BOPS, Inc. offers flexible licensing options including multi-use, per-use and single-use licenses.

About BOPS

Based in Mountain View, Calif., BOPS, Inc. develops and licenses a fully scalable, synthesizable DSP architecture that is programmable and reusable for evolving communications, mobile multimedia and wireless applications. BOPS DSP architecture, cores, compilers, system tools and complete SOC designs offer total life-cycle solutions and rapid time-to-market. While providing the highest performance in the industry, BOPS(R) cores are DSP co-processors to ARM, MIPS and other hosts and are supported by an extensive alliance of hardware, software, tools and design partners. For more information, please visit http://www.bops.com.

Note to editors: BOPS and ManArray are registered trademarks of BOPS, Inc. SOC in a Box, MICoRay, MoCARay, and WirelessRay are trademarks of BOPS, Inc. All other brands or product names are the property of their respective holders.