Azuro's PowerCentric Reduces Power Consumption for ARC(TM) Configurable Subsystems and Cores by More Than 20 Percent.ELSTREE, England & MOUNTAIN VIEW, Calif. -- ARC International This article is about the publicly traded processor company. For the privately held French housewares company of the same name, see ARC International (household). plc. (LSE LSE - Language Sensitive Editor :ARK) and Azuro, Inc. today announced that Azuro's PowerCentric low power methodology now is available for ARC(TM) licensees designing audio- or video-centric digital chips for embedded applications An application that permanently resides in an industrial or consumer device. Providing some type of control function and/or user interface, the software is typically stored in a non-volatile memory such as ROM or flash memory. . With the use of Azuro's PowerCentric in existing Cadence, Synopsys or Synplicity design flows, customers of the configurable ARC Media Subsystems and CPU/DSP processors can reduce power consumption of the ARC-Based(TM) logic by more than twenty percent(1). This complements the existing ability of ARC licensees to achieve the industry's lowest power consumption of any 32-bit configurable processor or subsystem through the use of ARC's patented ARChitect configuration tool, where unneeded elements can be eliminated to dramatically reduce power usage. "ARC continuously strives to offer best-in-class configurable solutions that fit the stringent needs of customers designing SoCs for power sensitive applications," said Peter Hutton, senior vice president of engineering at ARC International. "By leveraging Azuro's PowerCentric low power methodology, licensees can further reduce power consumption of ARC's configurable subsystems and processors by more than 20% without impacting processor footprint." Azuro's PowerCentric uniquely combines clock gating and clock buffering into one unified low power clock implementation solution which completely replaces clock tree synthesis in existing industry design flows. A demonstration of the technology on an ARC(TM) Video Subsystem will be available to qualified companies at the 2006 Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ) in San Francisco San Francisco (săn frănsĭs`kō), city (1990 pop. 723,959), coextensive with San Francisco co., W Calif., on the tip of a peninsula between the Pacific Ocean and San Francisco Bay, which are connected by the strait known as the Golden . Interested parties should contact Azuro for more information. Ashutosh Mauskar, vice president of product marketing for Azuro, said, "By incorporating Azuro's PowerCentric into design flows for ARC's products, our mutual customers are able to deploy extremely power efficient silicon. We are happy to be a low power solution for ARC licensees and look forward to future collaborations with the leader in configurability." Availability Azuro's PowerCentric solution for ARC's configurable subsystems and processor families is available now from Azuro, Inc. About ARC International plc ARC International is the world leader in configurable subsystems and CPU/DSP processors that are used by semiconductor companies worldwide for next-generation system-on-chip (SoC) design. ARC's patented configurable processor technology enables the development of consumer, networking, mass storage and other cost-sensitive devices that are smaller and provide a higher degree of differentiation over what can be created using "fixed architecture" core alternatives. ARC International maintains a worldwide presence with corporate and research and development offices in California and Elstree, UK. For more information visit www.ARC.com. ARC International is listed on the London Stock Exchange London Stock Exchange London marketplace for securities. It was formed in 1773 by a group of stockbrokers who had been doing business informally in local coffeehouses. as ARC International plc (LSE:ARK). About Azuro Azuro, Inc. is a provider of innovative electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) solutions that significantly reduce the power consumption of digital semiconductor chips. Founded in 2002, the privately held company privately held company A firm whose shares are held within a relatively small circle of owners and are not traded publicly. is headquartered in Mountain View, Calif., with a development center in Cambridge, UK. For further information, visit www.azuro.com or call (650) 237-3500. Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. ARC and the ARC logo are trademarks or registered trademarks of ARC International. All other brands or product names contained herein are the property of their respective owners. This press release may contain certain "forward-looking statements forward-looking statement A projected financial statement based on management expectations. A forward-looking statement involves risks with regard to the accuracy of assumptions underlying the projections. " that involve risks and uncertainties. For factors that could cause actual results to differ, visit the company's Website as well as the listing particulars filed with the United Kingdom Listing Authority and the Registrar of Companies The introduction to this article provides insufficient context for those unfamiliar with the subject matter. Please help [ improve the introduction] to meet Wikipedia's layout standards. You can discuss the issue on the talk page. in England and Wales England and Wales are both constituent countries of the United Kingdom, that together share a single legal system: English law. Legislatively, England and Wales are treated as a single unit (see State (law)) for the conflict of laws. . (1) Results were achieved after layout and timing closure using the Azuro PowerCentric solution on an ARC(TM) Video subsystem core in a 130nm process. Results were compared against an industry standard EDA flow which included clock gating and clock tree insertion. |
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