Azuro's PowerCentric(TM) Adopted by NVIDIA.

PowerCentric Reduces Power and Increases Design Team Productivity for NVIDIA

SANTA CLARA, Calif. -- Azuro, Inc. the provider of advanced clock implementation tools for nanometer (nm) chip design, today announced that NVIDIA Corporation, the worldwide leader in programmable graphics processor technologies, has entered into a multi-year agreement to purchase Azuro's PowerCentric[TM]. NVIDIA selected PowerCentric after a successful evaluation that demonstrated PowerCentric's ability to reduce power and also meet complex variability-driven clock tree implementation requirements.

"For NVIDIA, we must deliver unmatched features and performance in our graphics, multi-media communication processors and application processors while meeting tight power budgets, performance and area constraints. Consequently, our designs contain extremely complex clock trees with multiple branches at the block level that also needs to be balanced for min./max. corners," said David Dumoulin, director of engineering at NVIDIA. "PowerCentric gives us the ability to implement superior clock trees inside our existing physical framework of EDA tools."

Azuro's PowerCentric is a clock tree synthesis and optimization solution that brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis, and statistical average-case dynamic power analysis, to deliver a completely unified clock implementation solution for advanced nanometer designs. PowerCentric delivers 15-25% power savings above and beyond traditional EDA flows and also supports concurrent multi-corner clock tree balancing and timing optimization.

"Designers spend a lot of time getting their clock implementation right, especially within challenging nanometer environments that demand low power, high speed, and high yields all at the same time," said Ashutosh Mauskar, vice president of product marketing for Azuro. "PowerCentric implements clock gating and clock buffering entirely within one unified step, operating at the placed-gates level in the design flow. This enables PowerCentric to explore a larger global solution space of clock gating topologies and make better power-timing-variability trade-offs than other industry solutions. We are very excited to be working with NVIDIA at the cutting edge of nanometer ASIC design."

About Azuro

Azuro, Inc. is a provider of advanced clock implementation tools for nanometer chip design. Azuro's flagship product, PowerCentric[TM], operates as a complete replacement for clock tree synthesis within digital design flows, comprehensively addressing power, timing, and variability within one unified optimization environment. Founded in 2002, the privately held company is headquartered in Santa Clara, California, with R&D offices in Cambridge, UK.

Azuro's technology has been in production use since early 2004 where it has been consistently proven to deliver significant reductions in total chip power consumption without any impact on chip size or performance. For further information, visit www.azuro.com or call 408-970-8200.

Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.