Axis Systems Announces Plans to Use Altera's New APEX Architecture in Xcite; Xcite With APEX Ships Later This Year.
SUNNYVALE, Calif.--(BUSINESS WIRE)--April 19, 1999--
Axis Systems, Inc., an EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. company focused on improving the verification process for electronic system-on-a-chip designs announced its plans to use Altera Corporation's (NASDAQ NASDAQ
in full National Association of Securities Dealers Automated Quotations
U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : ALTR) Advanced Programmable Embedded MatriX (APEX(tm)) architecture in future versions of Axis' Xcite(tm) product family, a design verification tool that includes a ReConfigurable Computing (RCC RCC - An extensible language. ) co-processor with Altera devices.
The new Altera technology improves Axis' customers' design verification flows by improving performance and allowing for more gate capacity.
Steve Wang, Axis' vice-president of marketing, said, "Altera is one of our most important partners. Our intention is to offer and improve our design verification product family, Xcite, using the latest Altera architectures as they become available."
Wang added, "Our Xcite hardware verification solution is designed to use the highest density devices available from Altera and currently simulates designs up to 4-million gates. We are integrating Altera's Quartus(TM) design environment into our product and plan to expand our gate capacity with Altera's APEX 20K devices."
Altera's APEX 20K programmable logic architecture is the first architecture to successfully integrate product-term and look-up table functionality along with embedded memory, to provide breakthrough System-on-a-Programmable-Chip(TM) integration. With device densities up to 1 million gates and enhanced in-system performance, the APEX architecture provides unsurpassed design efficiency and total control of system design.
The first APEX 20K device, a 400,000-gate EP20K400, is shipping and is supported by Altera's Quartus design environment and backed by a full complement of intellectual property cores, including processors, communications blocks and bus interface functions from Altera and from the Altera Megafunction Partner Program (AMPP AMPP Apache, MySQL, PHP and Perl
AMPP Actual Medicinal Product Pack (UK)
AMPP Advanced Materials and Processing Program (SM)) member companies.
About APEX In Axis Systems' Xcite RCC Co-processor
For Axis Systems' application, Altera's APEX 20K family provides leading edge performance and density in a programmable logic device See PLD. . The combination of product-term and look-up table functionality, combined with abundant embedded memory, enables high-speed verification of a wide range of functions, from combinatorial logic to complex state machines.
The System-on-a-Programmable-Chip functionality provided by the APEX architecture is supported by Altera's fourth-generation development environment, Quartus, which includes a powerful debug capability called SignalTap(TM). This tool combines the functionality of a logic analyzer with the on-chip power of an intellectual property core to provide at-speed analysis and debug of Altera's programmable logic devices. With SignalTap, the signals inside even the most complex BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. packages can be isolated, tested and debugged with unprecedented accuracy and ease.
More About Xcite
The Xcite RCC co-processor coupled with functional verification and debugging software improves design verification throughput by orders of magnitude over software-only simulators. Xcite addresses behavioral, RT-level and gate-level simulation and verification of million-gate plus designs.
The Xcite RCC co-processor fits inside a Sun(tm) Microsystems (NASDAQ: SUNW SUNW Sun Microsystems, Inc (former stock symbol; now JAVA)
SUNW Stanford University Network Workstation (Sun Microsystems, Inc) ) Ultra(tm) 30 or Ultra 60 workstation and connects directly to its PCI (1) (Payment Card Industry) See PCI DSS.
(2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). backplane. Axis also offers the Xcite software simulator. This product operates with or without the RCC co-processor.
Price and Availability
Xcite-1000 for designs of up to 4-million gates is shipping now with Altera's FLEX(tm) 10K250 programmable logic devices using BGA packaging. Axis plans to ship Xcite with APEX architecture late this year.
Xcite-1000 includes a software simulator and RCC compiler. The Company estimates that verification with Xcite's RCC co-processor costs less than 10 cents (USD USD
In currencies, this is the abbreviation for the U.S. Dollar.
The currency market, also known as the Foreign Exchange market, is the largest financial market in the world, with a daily average volume of over US $1 trillion. ) a gate.
About Axis Systems
Axis Systems, Inc. is a technology leader in the logic design verification market. Founded in 1996, the company offers breakthrough technologies and high-speed products to verify electronic systems and systems-on-a-chip.
Contact information: Axis Systems, Inc., 209 Java Drive, Sunnyvale, CA 94089, 408-588-2000, FAX: 408-588-1662, firstname.lastname@example.org, www.axiscorp.com.
Acronyms: BGA: Ball grid Array “BGA” redirects here. For other uses, see BGA (disambiguation).
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. EDA: Electronic Design Automation FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. : Field Programmable gate Array See FPGA. RCC: ReConfigurable Computing RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; : Register-Transfer Level or RT-level
Notes to Editors:
A photo or electronic image of Axis' RCC co-processor and a white paper on RCC technology are available on request.
Contact for inquiries: Axis Systems, Inc., 209 Java Drive, Sunnyvale, CA 94089, 408-588-2000, FAX: 408-588-1662, email@example.com or visit www.axiscorp.com, Attn.: Steve Wang x111
Xcite is a trademark of Axis Systems, Inc. All other trademarks are the property of their owners.