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Axcelis Introduces Photoresist Dry Strip System for Low-k Dielectrics.


Business Editors

BEVERLY, Mass.--(BUSINESS WIRE)--May 27, 2003

New ES3Lk provides unique process capability for damage-free cleaning of low-k materials

Axcelis Technologies Axcelis Technologies, Inc. NASDAQ: ACLS engages in the design, manufacture, and servicing of capital equipment for the semiconductor manufacturing industry worldwide. , Inc. (NASDAQ NASDAQ
 in full National Association of Securities Dealers Automated Quotations

U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on
: ACLS ACLS
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) today introduced the ES3Lk, a novel 300mm resist stripping system specifically designed to support the integration of low-k dielectric materials Dielectric materials

Materials which are electrical insulators or in which an electric field can be sustained with a minimal dissipation of power. Dielectrics are employed as insulation for wires, cables, and electrical equipment, as polarizable media for
. The ES3Lk is the industry's first plasma stripping system to provide a zero-damage process for low-k materials, capping layers and etch stops used in low-k integration schemes through the 45nm technology node See technology generation. . A stand-alone dry strip system, the ES3Lk gives chipmakers up to 25% lower cost of ownership than in situ In place. When something is "in situ," it is in its original location.  etch/strip tools, where the etch and strip process are performed in a single process chamber.

Photoresist removal processes represent one of the top five challenges to low-k integration, according to according to
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 the International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry Associations of the US, Europe, Japan, . This is because conventional dry cleaning processes introduce latent damage in low-k materials, leading to adverse changes in the dielectric and the material's physical properties; these changes are especially evident after a wet cleaning step.

"Low-k dielectrics can only improve device performance if chipmakers have the tools and processes that enable them to overcome the unprecedented integration challenges associated with these sensitive materials," said Jan-Paul van Maaren, vice president and general manager of Axcelis Curing and Cleaning Systems. "By working closely with our customers, industry research laboratories and low-k materials suppliers, Axcelis has been able to deploy non-damaging chemistries on a robust dry strip platform. The result is a new process that preserves the insulating and structural properties of the low-k materials that chipmakers are adopting for dual-damascene chip designs, both today and for years to come."

The result of several years of focused R&D activity and extensive field verification, the Axcelis ES3Lk is a new isotropic Refers to properties that do not differ no matter which direction is measured. For example, an isotropic antenna radiates almost the same power in all directions. In practice, antennas cannot be 100% isotropic.  dry strip system that maintains the lowest k-effective value for integrated back-end-of-line (BEOL BEOL Back-End-Of-Line
BEOL Bent's Old Fort National Historic Site (La Junta, Colorado)
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) dielectric stacks. Compatible with subsequent wet cleaning steps, the ES3Lk process can be used with virtually all dense and porous low-k materials, allowing customers to extend the process across several technology generations.

Based on Axcelis' FusionES3 platform, which has been adopted by chipmakers worldwide for its reliability, productivity and process performance, the ES3Lk gives chipmakers the ability to meet high-volume production goals. The tool is a stand-alone dry strip system, which offers up to 25 percent lower cost of ownership compared to integrated in situ etch/strip systems. The system's unique downstream microwave chamber design provides consistent strip rates, high process uniformity and excellent selectivity to low-k materials, while integrated load lock chambers ensure process integrity.

Presentation and Reception at IITC IITC International Indian Treaty Council
IITC International Interconnect Technology Conference
IITC International Imaging Technology Council
IITC Integrated Information Technology Corporation
IITC Intertribal Information Technology Company
 

Axcelis technologists will be available to discuss the ES3LK technology during IEEE's International Interconnect Technology Conference (IITC) being held June 2-4, 2003, in Burlingame, Calif. Customers and press are invited to visit the Axcelis booth, #212, during the two-day conference. In addition, Axcelis will present co-authored papers on the ES3Lk technology during its IITC process seminar on June 2. Press interested in attending the reception should contact Stacy Grisinger at Loomis Group, +1 (617) 638-0022 or grisingers@loomisgroup.com.

About Axcelis Technologies, Inc.

Axcelis Technologies, Inc., headquartered in Beverly, Massachusetts, provides innovative, high-productivity solutions for the semiconductor industry. Axcelis is dedicated to developing enabling process applications through the design, manufacture and complete life cycle support of ion implantation, rapid thermal processing Rapid Thermal Processing (or RTP) refers to a semiconductor manufacturing process which heats silicon wafers to high temperatures (up to 1200 C or greater) on a timescale of several seconds or less. , and cleaning and curing systems. Axcelis Technologies has key technology centers in Beverly, Massachusetts, and Rockville, Maryland as well as in Toyo, Japan through its joint venture, SEN. The company's Internet address is: www.axcelis.com.

Forward-Looking Statements

This press release includes certain statements, known as "forward-looking statements," which express the current expectations of Axcelis management. Certain risks and uncertainties could cause actual results to differ materially from those currently anticipated as expressed in this press release. Among other factors, such risks and uncertainties include the continuing demand for semiconductor equipment, relative market growth, continuity of business relationships with major customers, competitive pressure on sales and pricing, increases in material and other production costs that cannot be recouped in product pricing and global economic and financial conditions. These risks and other risk factors relating to Axcelis are described more fully in the most recent Form 10-K Form 10-K

A report required by the SEC from exchange-listed companies that provides for annual disclosure of certain financial information.


Form 10-K

See 10-K.
 filed by Axcelis and in other filings from time to time with the Securities and Exchange Commission.
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Publication:Business Wire
Geographic Code:1USA
Date:May 27, 2003
Words:710
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