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Aware Inc. Announces Availability Of ASIC Cores For DSL Chipsets; Aware's ASIC Cores Will Accelerate DSL Development for Chip Makers.


BEDFORD, Mass.--(BUSINESS WIRE)--Oct. 6, 1998-- Aware Inc. (NASDAQ NASDAQ
 in full National Association of Securities Dealers Automated Quotations

U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on
:AWRE AWRE Atomic Weapons Research Establishment
AWRE Australian Workshop on Requirements Engineering
AWRE Automatic Write Reallocation Enable
), a worldwide leader in DSL (digital subscriber line See DSL.

(communications, protocol) Digital Subscriber Line - (DSL, or Digital Subscriber Loop, xDSL - see below) A family of digital telecommunications protocols designed to allow high speed data communication over the existing copper telephone lines between end-users and
) technology for high-speed Internet access, today announced the availability of ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  (application specific integrated circuit) cores for silicon providers and equipment manufacturers who wish to rapidly integrate full-rate ADSL or DSL-Lite technology into their product lines while reducing their development risk.

Aware's field-proven, highly specialized cores enable "system on a chip" designers to treat complex ADSL See DSL.

ADSL - Asymmetric Digital Subscriber Line
 functions as easy-to-use building blocks that may be incorporated into application specific integrated circuits. The cores enable silicon providers and equipment manufacturers to leverage Aware's experience and expertise to dramatically reduce development risks and time to market.

Immediately available in multiport configurations for high-port density solutions are Aware's Alphaeus and Zephyr cores.

The Alphaeus core implements the transition from ADSL data to ATM (asynchronous transfer mode See ATM.

(communications) Asynchronous Transfer Mode - (ATM, or "fast packet") A method for the dynamic allocation of bandwidth using a fixed-size packet (called a cell).

See also ATM Forum, Wideband ATM.

ATM acronyms.

Indiana acronyms.
) cells enabling ATM over ADSL transmissions per ANSI (American National Standards Institute, New York, www.ansi.org) A membership organization founded in 1918 that coordinates the development of U.S. voluntary national standards in both the private and public sectors. It is the U.S. member body to ISO and IEC.  T1.413 and the ITU I.432 standards. Utopia Level 1 or 2 interfaces are provided per the ADSL Forum Utopia Specifications.

The Zephyr core implements the protocols and data integrity functions required for standard-compliant ADSL solutions. This highly configurable core supports all framing, error correction and interleaving interleaving - sector interleave  modes required by ANSI T1.413 and the upcoming ITU G.Lite standard.

Alphaeus and Zephyr are the first in a family of ASIC cores that Aware has developed to provide the functionality of a complete, standard-compliant DMT See DSL.  modem. Each core is available in multiport configurations for developers of central office and digital loop carrier In telephone communications, a technology that increases the number of channels in the local loop by converting analog signals to digital and multiplexing them back to the end office.  solutions and single port configurations for designers of customer premise and PC modem solutions.

"As a technology leader in the ADSL industry, Aware aims to provide standard-compliant solutions in readily useable forms that accelerate the deployment of true high-speed Internet access using ADSL," said Michael Tzannes, president and chief executive officer of Aware.

Lucent Technologies Microelectronics Group is licensing Aware's Zephyr core to accelerate Lucent's deployment of its WildWire(tm) DSL modem communications chip technology.

"Aware's Zephyr core is easily integrated within Lucent's WildWire modem chipset solution," said Bob Rango, general manager of new business initiatives with Lucent's Microelectronics Group. "The resulting WildWire DSL chipset will be brought to market quicker as a result of this technology."

These highly optimized cores are available in VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction.  and Verilog hardware description languages as well as gate-level netlists targeted at specific semiconductor manufacturing processes. Aware supports the integration of its solutions through the circuit fabrication, verification, test and deployment process.

In addition to ASIC cores, Aware's technology and software solutions include system models and designs, run-time software and board-level designs. These technology solutions are available or will be available for each of the company's three DSL applications - asymmetric digital subscriber line (communications, protocol) Asymmetric Digital Subscriber Line - (ADSL, or Asymmetric Digital Subscriber Loop) A form of Digital Subscriber Line in which the bandwidth available for downstream connection is significantly larger then for upstream.  (ADSL), DSL-Lite, and very-high-speed digital subscriber line (VDSL). Each of these applications implements one of two modulation techniques for transmitting data - discrete multitone (DMT) or discrete wavelet multitone (DWMT).

About Aware

Aware Inc. designs, develops, licenses and markets DSL technology that enables high-speed Internet access over existing telephone networks. The company licenses its intellectual property and software to semiconductor manufacturers and equipment manufacturers who manufacture and sell integrated circuits or equipment incorporating Aware technology. Aware markets its technology to systems companies to encourage them to design Aware technology into their products, and to service providers to encourage them to deploy new broadband services based on Aware's technology. Aware is a member of RAPID (Reusable Application-Specific Intellectual Property Developers) industry consortium. More information about Aware can be found on the World Wide Web at http://www.aware.com.

Note to Investors:

This press release contains certain statements of a forward-looking nature relating to future events or the future financial performance of Aware. Important factors that could cause actual results to differ materially from those indicated by such forward-looking statements include the risks described in various SEC filings that Aware, Inc. has made on its Forms S-1, 10-K, and 10-Q, which factors are incorporated herein by reference.
COPYRIGHT 1998 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1998, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1USA
Date:Oct 6, 1998
Words:655
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