Avoiding differential pair: routing violations: take these steps to recognize and avoid layout mistakes when routing high-speed differential pairs.

A previous article (1) addressed several layout guidelines for high-speed differential pairs, such as maintaining parallelism and symmetry between two complementary traces. This article focuses on certain mistakes that can occur when routing or designing high-speed differential networks and how to avoid them. FIGURE 1a shows differential pair traces routed from plated through-hole component pins in a way that violates the lateral symmetry rule, while FIGURE 1b illustrates a superior symmetrical routing approach.

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The symmetry rule as applied to placing via pairs is demonstrated by FIGURE 2. Figures 2a and 2b depict differential signals connected from top to bottom layers by means of via pairs. However, in Figure 2a the via placements lack symmetry (e.g., they are not positioned in similar locations), and are thereby undesirable. Figure 2b shows the preferred method, with the via pair placed in the same relative positions along the differential traces, achieving symmetry.

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FIGURE 3 illustrates a portion of a signal layer with a reference plane with gaps due to multiple powers. Three layout mistakes are also marked. Violation 1 is due to routing of high-speed signals over a plane split. Frequently, the reference plane is a solid continuous ground layer well-suited for high-speed PCBs. However, there are also cases when the reference is a power plane with multiple power islands and associated boundary gaps. It is undesirable for high-speed signals to cross a plane gap, because this can disrupt the common-mode current return paths, degrade signal quality, and increase EMI and power/ground bounce. For similar reasons, routing over other types of plane voids (such as via and through-hole clearances) should be avoided if possible. Avoiding routing over plane slots also applies to high-speed single-ended signals, for which it could be even more critical because plane gaps divert the return signal path, add to trace inductance and increase crosstalk.

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Violation 2 relates to preventing stubs whenever feasible because they can also degrade signal quality and influence EMI. Violation 3 refers to the blue trace where parallelism is violated. The green trace shows a preferred routing for that section. Disregarding parallelism requirements can result in impedance discontinuities, adversely affect signal quality, contribute to length mismatch and skew.

Analyses of material composition of flame-retardant epoxy-glass laminate sheets (FR-4) leads to interesting routing considerations. FIGURE 4 shows formation (2,3) of FR-4 by fiberglass bundles (in gray) embedded in solidified resin (yellow). Actually, the natural color of fiberglass (which provides mechanical stability to the core or prepreg laminate) is normally white, and resin (which fills spaces between fibers forming a sturdy smooth surface matrix for supporting PCB structures such as traces and vias) is pale yellow. The electrical properties of FR-4 can vary with the ratio (4) of the localized fiber to resin.

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The relative dielectric constant (Er) of FR-4 can range (5) from 4.0 to 4.5. However, the Er for pure resin epoxy is ~3.8 and for pure (E-glass) fiberglass is ~5.8 at 1 MH[z.sup.3]. Subsequently, due to such inhomogeneous material characteristics, a trace routed over sections of mostly resin can experience a different Er than a trace routed over regions which contain mainly fiberglass bundles. This can lead to undesirable skew, since the effective Er of a substrate influences the impedance and velocity (6) of outer layer (microstrip) and inner (stripline) traces. This concept is further illustrated by FIGURE 5.

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Differential pairs having long horizontal or vertical traces (Figure 5a and 5b) are more susceptible to such skew than traces that include diagonal sections (Figures 5c and 5d). For example, in Figure 5a the green trace is routed directly over a fiberglass (Er ~5.8) section, whereas the red trace is over substrate area containing resin epoxy (Er ~ 3.8). This can lead to skew, as explained. Similar reasoning applies to Figure 5b with long horizontal traces. However, in Figure 4c, which is mostly diagonal, and Figure 4d, which is routed completely diagonally, the inhomogeneous dielectric effects are averaged out. Hence, for high-speed applications it can prove beneficial to route long differential traces diagonally (in order to distribute the effects of fiberglass weaves and resin rich dielectric regions) rather than vertically or horizontally (e.g., parallel to the X or Y axes of the PCB layer).

Furthermore, to minimize skew and to achieve accurate timing margins, length matching is a key consideration (1,7). FIGURE 6 demonstrates how the inner package trace lengths (L1_pkg and L2_pkg) and the PCB routed trace lengths (L1_PCB and L2_PCB) need to be accounted for optimum length match.

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Additionally, there are often routing constraints on the minimum and maximum trace lengths and impedance tolerance. Termination of differential pairs is also recurrently required to minimize noise and reflection on the lines. The optimum trace length limits, impedance range, and termination values (8) for achieving best signal quality and timing margins can be effectively ascertained by means of simulation. FIGURE 7 shows a topology that includes a differential driver (U1), transmission lines (T1, T2, T3 and T4), termination resistor (Rt) and a differential receiver (U2).

[FIGURE 7 OMITTED]

To produce accurate results in high-speed simulations, it is often necessary to model the transmission lines as lossy (rather than loss-less) since the PCB dielectric and conductor losses may degrade signal amplitude, edge rates, noise margins and system timing (6). However, it can prove expedient to recognize when the line losses are negligible allowing modeling simplifications and enhancement of simulation efficiency (9).

In Figure 7, the inner topology of the chip package (which can include die pads, bond wires, trace segments, vias, etc.) are not shown. However, when simulating it is strongly recommended to obtain the package trace lengths (or equivalent parasitic) for the driver and receiver models and take them into account. By accurately incorporating the effects of inner package traces (and other parasitic sources), it is possible to simulate from pads of the driver to pads of the receiver buffers leading to more reliable simulation outcome (as compared to results when package effects are ignored).

One way of showing the inner package traces has been illustrated by Figure 6, and it has already been noted that in some cases the package parasitic model may be more involved than a simple trace segment. FIGURE 8 depicts another way of representing the driver and receivers parasitics in a topology.

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When carrying out high-speed PCB common clock or source synchronous timing analyses, involving parameters such as signal propagation delay, flight times, driver's Tco (clock-to-output delay), receiver's setup and hold times; it is important to distinguish whether these parameters are defined with respect to buffer pad (at the die) or the IC pin.

The block representing the package parasitic in Figures 8a and 8b may be a lumped RLC circuit, a distributed transmission line (suitable for Spice simulations), or a TOPSPEC (for XTK simulations). The complexity of package model can vary significantly. A listing of the elements that can contribute to package resistance, capacitance and inductance parasitic (R_PKG, C_PKG, and L_PKG) for tape ball grid array, plastic BGA, flip-chip BGA, quad flatpack, and dual-in-line package are listed below:

TBGA: A trace and ball (note: multilayer TBGA can also contain vias inside the package).

PBGA: Bond wire, package trace, via and the ball.

FCBGA: Solder bump, a trace, a via and the solder ball.

QFP: Bond wire and the pin.

DIP: Bond wire and the lead.

For each of the above, the die trace can add a small amount of parasitic, too.

The signal speed (edge rates) also strongly influences the required complexity of the package modeling for accurate simulation. The equivalent parasitic parameters for inner package topology and the IC leads may be obtained from various sources such as device's data sheet, Spice or IBIS models, etc. Frequently, for high-speed simulations, it is preferable for the package parasitics to be modeled in distributed format (e.g., characterized as transmission line of some length, impedance and velocity), rather than as a lumped RLC structure (10).

ACKNOWLEDGMENTS

I am grateful to my colleagues Peter Arnold, Jeremy Plunkett, Danwei Xue, Dean Gonzales, Edward Tsuei and Mahrokh Esfandiary for valuable discussions.

REFERENCES

(1.) Abe Riazi, "Differential Signals Routing Requirements" PCD&M, February 2004, pp. 22-23.

(2.) Martin W. Jawitz, Printed Circuit Board Materials Handbook, McGraw-Hill, 1997, pp. 5.10-5.11.

(3.) Howard Johnson and Martin Graham, High-Speed Signal Propagation Advanced Black Magic, Prentice Hall, 2003, pp. 271 273.

(4.) Eric Bogatin and Steve Zimmer, "Achieving Impedance Control Targets" PCD&M, April 2004, pp. 28-31.

(5.) Eric Bogatin, Signal Integrity--Simplified, Prentice Hall, 2004, pp. 129-130.

(6.) Stephen H. Hall, Garrett W. Hall, James A. McCall, High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices, John Wiley and Sons Inc., 2000, pp. 16-17,74 and 312-313.

(7.) Abe Riazi, "Differential Signals Routing Requirements, Part II," PCD&M, March 2004, p. 20.

(8.) Douglas Brooks, Signal Integrity Issues and Printed Circuit Board Design, PrentFce Hall, 2003, pp. 262-265.

(9.) Abe Riazi, "Engineer's 'rule of thumb' simplifies PCB signal integrity," EE Design, Aug. 19, 2002.

(10.) Lee Ritchey, Right the First Time: A Practical Handbook on High Speed PCB Design, vol. 1, Speeding Edge, 2003, pp. 229-230.

ABE (ABBAS) RIAZI holds a Ph.D. in electrical engineering and is a senior signal integrity engineer with ServerWorks, A Broadcom Co. (serverworks.com). He can be reached at [e-mail].