Avoiding board bounce: addressing root causes of digital noise and test instability.

Test stability and signal fidelity problems during in-circuit digital testing have long plagued test engineers. Progressively higher-speed logic families and larger integrated circuit (IC) packages continue to exacerbate these problems. What are the most common root cause mechanisms behind these problems and how can you deal with them before they ruin your day?

The most common problem affecting stability of digital in-circuit tests is ground bounce between the device-under-test (DUT) and the test system. The worst challenge is many digital signals connecting the DUT to the test system switching simultaneously. Large ICs can exhibit ground bounce problems during regular in-circuit library tests; however, boundary-scan tests (the test method of choice for complex ICs) cause most ground bounce problems today.

Signal fidelity problems result from numerous sources, but the greatest source is controlled by the test engineer: the interconnection path between the DUT and the test system. Dealing with signal fidelity problems should only be attempted after ground bounce has been tamed--because many of them will go away as a result of solving ground bounce.

What Is Ground Bounce?

Ground bounce experienced during in circuit digital testing is a transient voltage differential between the test system ground and DUT ground. It results from current flowing through the non-zero impedance of the fixture ground path between the test system and the DUT. The inductance of the path is almost always more of a problem than the resistance of the path! Figure 1 illustrates basic in-circuit digital test ground bounce.

[FIGURE 1 OMITTED]

When the DUT output switches from low to high, the current Ircv must flow to charge the capacitance Crcv (tester + fixture capacitance). This current returns to the DUT as Ignd through fixture ground wiring. The current's rise time is limited by the path inductances, Lrcv and Lgnd. (In general, Lrcv is larger than Lgnd, because of the parallel ground paths.) The voltage that develops across Lrcv is inconsequential, reflecting the receiver input signal rise time limiting. The voltage across Lgnd, Vlg, is referred to as ground bounce.

Assume that the driver in Figure 1 is holding a static level of zero volts relative to test system ground. If Zin on the DUT is large (typical of a logic gate input), the current Idrv will be small, and little voltage will develop across Ldrv due to ground bounce. The DUT logic gate input, referenced to DUT ground, will see the ground bounce voltage Vlg as an input signal. If Vlg is large enough to cross the logic gate switching threshold, a test problem may result. This result is especially true if the logic input signal is a state-determining signal such as a dock, strobe or asynchronous reset.

Dealing with Ground Bounce

Figure 1 sheds considerable light on reducing ground bounce. Larger numbers of DUT outputs switching in unison will make ground bounce worse, as will larger voltage swings on the DUT and faster switching speeds. Increasing Lrcv will decrease ground bounce problems. Decreasing Crcv will reduce ground bounce problems but is difficult to do. Reducing fixture ground impedance, Lgnd, is effective and desirable. Lowering Zin and raising Ldrv can reduce ground bounce effects in some cases. Let's take these individually.

Simultaneous Switching

Simultaneous switching problems are common in boundary-scan tests but can be mitigated with relative ease on some in-circuit test systems.

Boundary-scan connection tests use the in-circuit tester DUT nodal access to verify that boundary-scan device I/O pins are connected to the DUT printed circuit board (PCB) as expected. Connection tests focus on one device at a time, with other boundary scan chain devices used to support the target device test. Some in-circuit testers allow breaking connection tests into segments to limit the number of pins in a given test without affecting test coverage. On systems without automatic segmenting, an experienced test engineer may be able to segment tests manually.

Simultaneous switching problems can also be reduced with improvements in the digital test patterns. Unlike most digital test methods, boundary-scan tests are insensitive to vector order. Smart vector pattern selection can reduce ground bounce by balancing "0" to "1" transitions with "1" to "0" transitions within a vector--limiting the current flowing between the DUT and the tester. If a tester does not automate this capability, performing it manually is extremely difficult.

Boundary-scan interconnection tests verify connectivity through the PCB from scan chain output pins to scan chain input pins. In many respects this process is "pure" boundary scan--the only DUT to test system connections required are the five boundary-scan (JTAG) lines. In-circuit test system nodal access can be detrimental for these tests as capacitive loading is still on these lines. This loading can be enough to cause ground bounce during interconnection tests. The most straightforward solution limits interconnection tests to lines without nodal access and tests all other signals with connection tests. This practice significantly reduces ground bounce without test coverage loss. Techniques for segmenting interconnection tests risk reduced shorts test coverage and are not recommended.

A software approach to reducing boundary scan ground bounce involves a minor change to the sequence of traversing TAP state diagram--by holding "TMS" low, the test will exit the "Update-DR" or "Update-LR" states to the "Run-Test/Idle" state before moving to the "Select-DR-Scan TMS high" state. This sequence will ignore extra clocks due to ground bounce provided TMS is not forced to a "1" state by ground bounce. If your in-circuit test system offers this option, it should always be used.

Logic Family Characteristics

When possible, the DUT designer should use logic families with the lowest possible output slew rates and drive currents. Many programmable logic devices allow setting output characteristics on a pin-by-pin basis, which helps reduce ground bounce.

Fixture Wiring Inductance

Raising inductance of fixture signal wires can effectively reduce ground bounce, providing that ground path inductance is kept low. Rise times (lower slew rates) of signals will slightly increase, and total current flowing between the DUT and the tester will be reduced. Longer fixture wires will accomplish this result at the expense of increased potential cross talk. In wire-wrap fixtures increasing wire inductance by adding ferrite beads to the signal wires is possible. Caution must be used because bead characteristics may make overdriving through a signal wire nearly impossible, a capability that may be required in another test.

Ground Inductance

Lowering ground path inductance has one possible downside: higher fixture cost. This challenge is usually compensated for by fewer test problems and less debug time required for the fixture.

Ensure that the DUT board has sufficient ground probe test pads. Ideally, a ground probe should be associated with, and proximal to, every state-determining signal. Also, one ground probe point should be available for every five to 20 signal pins, depending on DUT switching speed. At high speed CMOS slew rates, one ground for every five signal pins that are simultaneously active in a test is a good rule of thumb. This directive includes probed signals that switch even if they are not connected to a receiver during test. Ground probe points should be distributed proportionally with signal pins--more ground pins should be used where signal pins are dense, even though this practice increases probe density.

Using a ground plane instead of ground wiring in a wire-wrap fixture will significantly reduce ground inductance. Use a ground plane to best advantage by populating every possible fixture ground to DUT ground connection point and every possible fixture ground to test system ground connection point. A well designed wireless fixture will further the ground bounce improvements achieved with a ground plane.

An alternative is to use twisted-pair wiring for all signals, again requiring many well-distributed ground access points. This technique reduces ground bounce because the return current will flow down the wire paired with the signal wire, which is a very low inductance path. This practice can be cost effective for small boards. For larger boards the added costs and the wire pack density problems can be formidable.

State-Determining Line Solutions

Ground bounce can frequently be reduced on affected signals. DUT board signal input impedance should be kept low whenever possible. For signals driven from another board in the product, input impedance should be the transmission line termination impedance; an AC termination is fine. For lines only used during in-circuit test, a low impedance to ground--10 to 50 ohms, for example--will be well within test system driver capability. Adding a small capacitance (100pF to 500pF) to ground from the input signal may be possible, either on the board or within the fixture. Adding a ferrite bead to the fixture wire can raise fixture inductance. If the state determining signal is driven by a signal on the DUT, the impedance is already low enough to not have ground bounce sensitivity.

Signal Fidelity Issues

Once ground bounce is addressed, some signal fidelity problems may still exist. These mostly involve overshoot, undershoot, ringing, cross-talk and similar transmission line concerns. The best approach is to treat the fixture signal lines as transmission lines.

Occasionally, people worry about signal quality issues on non-state-determining signals--address and data busses, for example. In practice, this issue occurs if the effects continue when the related state-determining signal is asserted--data strobe, for example. Continuing effects are seldom seen in in-circuit test applications because the test rates are relatively slow (generally 1MHz to 10MHz).

The best approach is for the test engineer to identify state-determining signals in advance of developing the fixture and test. Ideally, this determination should be done in conjunction with the board designer--first, because the designer can usually identify the lines quickly and, second, because the test engineer may be able to influence design changes to improve test.

When possible, match the transmission line characteristics of the test system and fixture to the DUT requirements. In a wire-wrap fixture, you may need to use twisted pair or coax wiring for a few signals. Wireless fixtures offer a clear advantage, as you can route critical signals as controlled impedance transmission lines. Each line should then be terminated with its characteristic impedance at the destination end, which may require the addition of parts on the DUT or in the fixture as close to the DUT as possible. Fixture termination is often easier and more robust in a wireless fixture than in a wired fixture.

Some signal fidelity problems require fixture electronics. The most common of these are the measurement of extremely high frequency clocks on the DUT board, testing low-level differential logic and accommodating special communication standards. This topic is beyond the scope of this article, except to say that planning for fixture electronics in advance is easier than squeezing them in after the fact.

Another, often overlooked, signal fidelity problem is floating digital inputs. Many boards have signals that come from another board or have a device upstream that can be disabled. These floating inputs are prone to oscillating, especially in CMOS parts. Ideally, all of these inputs would have a pull up or pull-down resistor on the DUT board. If not, the test engineer should handle these signals by adding a pull-up/down resistor in the fixture or assuring that the line is always driven by the test system during in-circuit digital testing.

Conclusions

Ground bounce is a serious problem for in-circuit digital testing, often causing test failures. These problems are most common during boundary scan tests. By understanding the ground bounce mechanism, addressing many of the elements and significantly reducing the effects are possible. Solid solutions involve the design of the DUT board, the test methods and the test fixture design--the board designer and the test engineer most easily and effectively achieve this solution through a cooperative effort.

Signal fidelity problems that ca use in -circuit digital test problems are generally the result of poor transmission line characteristics of the tester/fixture/DUT environment. These problems are also best resolved by a cooperative effort between the board designer and the test engineer. The DUT board design and the fixture design are the most important elements in creating clean signal paths.

Phil King and Ray Balzer are both with Agilent Technologies, Loveland, CO; e-mail: [e-mail].