Avery Design and GDA Technologies Introduce MaxCov for PCI Express Compliance Verification.Business Editors/High-Tech Writers ANDOVER, Mass.--(BUSINESS WIRE)--June 9, 2004 Avery Design Systems Inc., an innovator in functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , and GDA GDA Grupo de Diarios de América (Spanish) GDA Global Development Alliance (USAID) GDA Guideline Daily Amount GDA Georgia Dental Association GDA Greenwich Dance Agency (England) Technologies, a leader in Silicon Intellectual Property (SIP) and Electronic Design Services (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ), today announced MaxCov, a comprehensive PCI Express A high-speed peripheral interconnect from Intel introduced in 2002. Note that although sometimes abbreviated "PCX," PCI Express is not the same as "PCI-X" (see PCI-SIG and PCI-X for comparison). As a result of the confusion, "PCI-E" or "PCIe" is the accepted abbreviation. interface verification testsuite that validates compliance to the PCI Express Checklists and ensures device interoperability. MaxCov extends the PCI-Xactor PCI Express verification products from Avery Design Systems. MaxCov is offered by Avery and GDA both independently and as part of GPEX, a suite of comprehensive design and verification IP solutions for PCI Express Endpoint, Root Complex, Bridge, and Switch designs. "GDA Technologies is the market leader of high-quality PCI Express design and verification IP. We are pleased that our partnership and over 10 person years investment in compliance testing can now be made available to the broader market in the PCI-Xactor PCI Express solution," says Chilai Huang, president of Avery Design Systems. "GDA's commitment to quality dictates that we apply rigorous verification standards," said Prakash Bare, vice president of IP business at GDA. "MaxCov is the direct result of our combined efforts in implementing comprehensive verification of the GPEX core. Using Avery's verification framework we can verify our GPEX core in different component configurations using highly reusable and customizable compliance tests offered in Verilog source code format." Key Features -- Tests developed in Verilog HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. -- Complete source code provided -- Tests target PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). SIG Compliance Checklists -- Users can edit and add new tests which are automatically added to functional test coverage tracking -- Tests based on advanced BFM BFM Berlin-Frankfurt-Münster (study group) BFM Bus Functional Model BFM British Furniture Manufacturers (UK) BFM Bonded Fiber Matrix (soil stabilization for erosion control) API supporting all component types -- Tests are reusable in all design topologies - from endpoint to switch to bridge using robust DUT DUT Dutch (language) DUT Device Under Test DUT Diplôme Universitaire de Technologie (French University Graduation in Technology) DUT Dalian University of Technology (also seen as DLUT) integration layer -- Testsuites provided for all layers (TL, DLL (1) See data link layer. (2) (Dynamic Link Library) An executable program module in Windows that performs one or more functions at runtime. DLLs are not launched by the user; they are called for by an executable program or by other DLLs. , PHY See physical layer and physical. ) with focus on configuration space, power management, hot plug, link training and lane negotiation, and system BIOS The BIOS on a PC motherboard. Contrast with BIOSs on the peripheral cards. See BIOS. operations -- User can select which tests to run - single, quick or full regression -- Dynamic test set execution based on Avery BFM and DUT capabilities supported -- Checklist assertions dynamically interact with test pass/fail status -- Complete functional test coverage report -- Tests can be run in directed or random modes About PCI-Xactor for PCI Express The PCI-Xactor for PCI Express Verification Solution is a complete verification solution consisting of Bus Function Model (BFM), SuperMonitor, and test suites and verification frameworks for functional verification of PCI Express components. The PCI-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their PCI Express compliant devices. Verification frameworks form complete testbench environments for endpoint, switch, and bridge designs. Verification engineers just need to replace an Avery BFM with their design and begin running comprehensive verification tests. The PCI-Xactor environment leverages advanced verification techniques of Avery's TestWizard product supporting complex data structures, transaction database, random generation, temporal property Noun 1. temporal property - a property relating to time property - a basic or essential attribute shared by all members of a class; "a study of the physical properties of atomic particles" checking, and coverage analysis. Key Features -- Complete set of fully functional BFMs and testbenches for every PCI Express component: Endpoints, Root Complex, Switch, and PCI/PCI-X to PCI Express Bridge -- Root Complex model provides the enumeration 1. (mathematics) enumeration - A bijection with the natural numbers; a counted set. Compare well-ordered. 2. (programming) enumeration - enumerated type. functions which allows the designer to verify designs earlier to catch driver setup problems -- Support for serial, 10b-bit symbol, and PIPE interfaces. -- Robust BFM API automates sending TLP/DLLP and controlling BFM device response and link state -- Inject errors and noise at various layers -- Test suites include compliance tests from PCI-SIG, random, error, and link-level stress tests -- Test are developed as self-checking, portable, and reusable on any type of design -- SuperMonitor verifies transaction ordering in N-port switch and bridge designs About PCI Express technology PCI Express technology is the new industry-standard I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output targeted to provide local connectivity across desktop, mobile, enterprise and communications platforms. PCI Express resides at the center of enterprise interconnect innovations anticipated across storage, networking, and clustering and workstations. Next-generation servers, utilizing PCI Express technology, will offer powerful and cost-effective computing platforms, scalable hardware building blocks, market-tested best-of-breed solutions, and enterprise-class reliability, availability, serviceability (system, design, hardware, software) Reliability, Availability, Serviceability - (RAS) Three key attributes of a computing system design. See reliability, availability, and serviceability. and manageability. About Avery Design Systems Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com. About GDA Technologies GDA Technologies, Inc. is a leading design services company specializing in embedded, networking and consumer electronic designs. GDA focuses on designing Systems, Boards, SOCs, ASICs, FPGAs and IPs from concept to product. GDA has successfully developed products in areas of Networking, Digital Video, Internet Appliances and Hand Held Solutions. GDA is headquartered in San Jose, Calif., and has satellite design centers in Boston, Sacramento, Singapore, Chennai and Bangalore, India. The GDA web site is www.gdatech.com. |
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