Avery Design Systems Revs PCI-Xactor Verification Solution for PCI Express 1.0 and PCI-X 2.0.Business Editors/High-Tech Writers ANDOVER, Mass.--(BUSINESS WIRE)--Feb. 19, 2003 Avery Design Systems, an Electronic Design Automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) provider of functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, solutions for ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and SOC design, today introduces support for the latest PCI Express A high-speed peripheral interconnect from Intel introduced in 2002. Note that although sometimes abbreviated "PCX," PCI Express is not the same as "PCI-X" (see PCI-SIG and PCI-X for comparison). As a result of the confusion, "PCI-E" or "PCIe" is the accepted abbreviation. and PCI-X (PCI eXtended) An enhanced PCI bus technology originally developed by IBM, HP and Compaq that is backward compatible with existing PCI cards. PCI and 32-bit PCI-X slots are physically the same, and PCI cards can plug into PCI-X slots. 2.0 standards in its PCI-Xactor Test Environment enabling higher levels of verification productivity and reuse across the comprehensive set of PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). standards. "PCI Express and PCI-X 2.0 deliver the next-generation I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output solutions for multiprocessor servers, Gigabit Ethernet An Ethernet standard that transmits at 1 Gbps. Used mostly to connect high-end workstations and servers as well as for network backbones, Gigabit Ethernet transmits full duplex from point to point using switches and half duplex in a shared environment (CSMA/CD) using a hub. , Fibre Channel and embedded networking," said Chris Browy, Vice President Sales and Marketing. "Our highly flexible and comprehensive PCI bus test environment delivers the next-generation verification solution that speeds PCI Express and PCI-X component and system compliance verification of endpoints, bridges, and switches utilizing any PCI bus standard and system topology." Avery Design is a member of the Intel(R) Developer Network for PCI Express Architecture. The PCI-Xactor Verification IP solution provides both analyzer and exerciser functions. The SuperMonitor Bus Analyzer is a passive model that snoops SNOOPS - Craske, 1988. An extension of SCOOPS with meta-objects that can redirect messages to other objects. "SNOOPS: An Object-Oriented language Enhancement Supporting Dynamic Program Reeconfiguration", N. Craske, SIGPLAN Notices 26(10): 53-62 (Oct 1991). all busses/links to profile bus activity and verify compliance to all PCI protocols using advanced assertion checking and coverage reporting. The Bus Analyzer also supports end-to-end system verification for bridge and switch designs. The SuperMonitor Bus Analyzer supports transaction verification through logging all bus transactions and verifying them for completion, data integrity, and ordering rules Ordering Rules The order in which Roth IRA assets are distributed. Assets are distributed from a Roth IRA in the following order: 1. IRA participant contributions 2. Taxable conversions 3. Non-taxable conversions 4. . "The Bus Analyzer can be dropped into any PCI system topology and immediately improve protocol verification and measure functional testing effectiveness," says Chilai Huang, President. The Bus Exerciser provides a PCI transaction API for the generation of directed and random bus traffic. The PCI-Xactor solution supports multiple master/slave BFMs each of which can be programmed to generate transactions or completions with normal or exceptional behaviors. The Bus Exerciser also supports the PCI SIG test suites that verify the behavior of the PCI devices. The PCI transaction API is supported in Verilog, C, and other popular hardware verification languages (HVL HVL, n See half-value layer. HVL half-value layer. ). Product Specific Features and Benefits -- PCI Express 1.0/PCI-X 2.0/PCI 2.2 compliant - Reusable environment for all PCI device configurations -- 32 or 64 bit PCI2.2 and PCI-X bus support -- PCI 33, PCI 66, PCI-X 66 (mode 1) PCI-X 133 (mode 1), PCI-X 66 (mode 2), PCI-X133 (mode 2), PCI-X 266 (mode 2), PCI-X 512 (mode 2) -- x1, x2, x4, x8, x12, x16, and x32 PCI Express lane support, PCI Express 2.5 Gbps support -- Complete PCI Express/PCI-X/PCI 2.2 compliance test suite - Facilitates PCI interface component-level compliance validation -- Bus Exerciser supports high-level PCI transaction API in Verilog, ANSI C, and HVLs - Enables easy integration into your system simulation environment -- Bus Analyzer supports customizable transaction logging and checking - Facilitates bridge and switch verification by verifying transaction completions and ordering rules involving multiple busses/links. -- Bus Analyzer supports built-in protocol checkers - Alerts designers of any PCI Express/PCI-X/PCI protocol violations and provides full assertion coverage reporting -- Bus Analyzer supports built-in functional coverage - Reports device and command utilization and bandwidth Package and Availability The PCI-Xactor Verification IP solution is offered with flexible packaging options. -- PCI Express Bus Analyzer -- PCI Express Bus Analyzer/Exerciser -- PCI/PCI-X Bus Analyzer -- PCI/PCI-X Bus Analyzer/Exerciser -- ALL PCI Bus Analyzer -- ALL PCI Bus Analyzer/Exerciser PCI Express and PCI/PCI-X Bus Analyzer are available for immediate delivery. The PCI Express and PCI/PCI-X Bus Exerciser will be available in Q1'03. Contact Avery for pricing information. The PCI-Xactor Verification IP solution works with ModelSim Version 5.6 and later, Cadence's NC-Sim and Verilog -XL releases 3.1 and later, and Synopsys' VCS (1) (Verilog Computer Simulator) See Verilog. (2) (Version Control System) See version control. 5.2 and later. About Avery Design Systems Avery Design Systems Inc. is a supplier of intelligent HDL-based functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com. |
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