Avery Design Systems Demonstrates Intelligent Testbench Automation and Parallel Simulation Solutions at Design Automation Conference.

Business/Technology Editors

ANDOVER, Mass.--(BUSINESS WIRE)--June 18, 2002

Avery Design Systems, a provider of functional verification solutions for ASIC and SOC design, demonstrated its SimLib Version 2.0 release including both the TestWizard and SimCluster products at the Design Automation Conference held June 10-14, 2002. SimLib provides advanced verification application extensions that integrate directly into popular HDL simulators including NC-Sim, VCS, and ModelSim.

"TestWizard and SimCluster target the two biggest verification-related problems facing design teams today - effective functional test development and debug and raw simulation throughput," said Chilai Huang, President. "Together TestWizard and SimCluster delivers 10X better performance, capacity, and productivity while completely leveraging today's best-in-class simulators and HDLs. We don't make another simulator or language, we make the ones that people already use better."

"SimCluster's scalable parallel simulation solution has already demonstrated up to 500% speedup over stand-alone VCS or NC-Sim simulations on large-scale system designs including a long-haul optical transport system and an edge router system," said Chris Browy, Vice President of Sales and Marketing. "The benefits of SimCluster include significantly faster turnaround time for large-scale simulation runs and elimination of the simulator capacity issue. This can save project teams significant time and money". SimCluster supports LAN-based and multiprocessor computing platforms.

SimCluster 2.0 features include:

-- Optimized inter-simulation synchronization for improved performance at both the RTL and gate-level

-- Remote C function call and data access mechanisms enabling increased transparency for HDL and C-based testbenches.

"TestWizard enables designers to verify designs 300% faster than conventional Verilog, VHDL, and C-based methods. TestWizard's advanced, native HDL-based transaction-level testbench automation runs on the industry's most popular simulators such VCS, NC-Sim, and ModelSim and delivers 2X better simulator efficiency compared to other proprietary verification-only language solutions in the market today," said Browy. TestWizard is a complete transaction-based testbench environment that lets users implement testbenches directly in an HDL and C. TestWizard supports HDL-based, transaction-level test generation functions including complex datastructures, pointers, and lists, constrained random case generation, transaction database with runtime queries, feature-set coverage analysis, coverage-driven adaptive testing, and temporal assertion checking.

TestWizard 2.0 Verilog and C/C++ features include:

-- A new transaction and record history database including advanced runtime queries that significantly improves complex out-of-order transaction-level result checking

-- Enhanced assertion checking features for temporal sequence detection and temporal expression analysis

-- Advanced Verilog-C synchronization methods supporting multi-threaded C-based testing

-- Remote C function call and data access mechanisms

TestWizard C/C++ based tests can be implemented as PLI/VPI applications or completely stand-alone processes.

"Verification is shaping up to be a hotly contested product segment in EDA. Avery is the only EDA vendor to provide all of the key testbench automation capabilities in a native HDL implementation that is portable across all popular simulators and HDLs used today," said Browy. "TestWizard already provides 'on-the-fly' simulation-based assertions commensurate with Accellera's pre-standard for formal property specification language, Sugar 2.0, which still has a ways to go before becoming an IEEE standard. Furthermore, the timeframe and outcome of EDA companies implementing the emerging SystemVerilog standard has shifted direction now that Synopsys has entered the picture."

Pricing and Availability

TestWizard for Verilog is available for immediate distribution under Solaris and Linux. Pricing starts at $7,500 for the node-locked, perpetual license version, and $4,500 for annual term licenses. SimCluster starts at $15,000 for the node-locked, perpetual license version, and $8,250 for annual term licenses. The SimLib product series works with Cadence's NC-Sim and Verilog-XL releases 3.1 and later, Synopsys' VCS 5.2 and later, and ModelSim Version 5.6 and later.

About Avery Design Systems

Avery Design Systems Inc. is a supplier of HDL-based functional verification products and service that enables dramatic testbench productivity and simulation performance improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems and free trial downloads are available at http://www.avery-design.com.