Avery Design Systems Accelerates ATPG/BIST Pattern Validation.ANDOVER, Mass. -- Avery Design Systems Inc., an innovator in functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , today announced improved support for simulation acceleration of ATPG/BIST pattern validation using its SimCluster parallel simulation solution with the release of automatic scan path scan path - (circuit design) A technique used to increase the controllability and observability of a logic circuit by incorporating "scan registers" into the circuit. Normally these act like flip-flops but they can be switched into a "test" mode where they all become one long shift partitioning and support for 64-bit Linux and Solaris platforms. SimCluster delivers simulation acceleration of 5-15X of RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; and gate-level designs using standard commercial simulators. "While functional gate-level simulation has been deemphasized in today's verification methodologies, ATPG/BIST validation is still essential but made overly difficult for today's multi-million gate designs due to the poor simulator performance and excessive process memory size requirements," said Chilai Huang, president of Avery Design. "SimCluster eliminates these bottlenecks by generating a multi-process, parallel ATPG/BIST simulation that runs in 1/10 the time and better exploits 32- and 64-bit compute platform resources." The auto-partitioner tool reads a flattened or hierarchical design netlist and ATPG/BIST testbench and partitions the database into multiple simulation targets. Scan-path partitioning enables the user to allocate one or more scan chains to different simulation partitions including the behavioral scan controller generated by the ATPG ATPG Automatic Test Pattern Generation ATPG Automatic Test Program Generator tool when writing out the patterns. This approach yields optimal performance by minimizing the communications overhead of parallel scan load, unload, and compare steps. SimCluster 3.0 also adds support for 64-bit Linux and Solaris operating systems Operating systems can be categorized by technology, ownership, licensing, working state, usage, and by many other characteristics. In practice, many of these groupings may overlap. which can be used in conjunction with simulators running in 64-bit mode. However the auto-partitioner may also be directed to target partitions that fit within 2-4 GB process size thus enabling the simulation to run on 32-bit platforms. About SimCluster SimCluster unleashes the power of distributed computing (1) The use of multiple computers networked throughout a wide geographical area, or the world via the Internet, in order to solve a single problem. See grid computing. (2) The use of multiple computers in an enterprise rather than one centralized system. for RTL and gate-level simulation and delivers scalable simulation performance of 5-15 X speedup or more. SimCluster simulates full-chip SOCs by allocating its subsystems to multiple tightly synchronized syn·chro·nize v. syn·chro·nized, syn·chro·niz·ing, syn·chro·niz·es v.intr. 1. To occur at the same time; be simultaneous. 2. To operate in unison. v.tr. 1. simulators running in parallel on 2 or more interconnected computers. SimCluster results are fully deterministic 1. (probability) deterministic - Describes a system whose time evolution can be predicted exactly. Contrast probabilistic. 2. (algorithm) deterministic - Describes an algorithm in which the correct next step depends only on the current state. and can be tuned for optimal performance. About Avery Design Systems Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com. |
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