Avery Design Accelerates SDF-Based Gate-Level Simulation.Business Editors/High-Tech Writers ANDOVER, Mass.--(BUSINESS WIRE)--June 9, 2004 Avery Design Systems Inc., an innovator in functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , today announced improved support for simulation acceleration of gate-level netlists using its SimCluster parallel simulation solution with the release of automatic partitioning of RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; and gate-level netlists including Standard Delay Format (SDF (Standard Data Format) A simple file format that uses fixed length fields. It is commonly used to transfer data between different programs. SDF Pat Smith 5 E. 12 St. Rye NY Bob Jones 200 W. Main St. Palo Alto CA Comma delimited "Pat Smith","5 E. ) files. SimCluster delivers simulation acceleration of 5-10X of RTL and gate-level designs using standard commercial simulators. "Our work with some of the world's leading computer systems, microprocessor, and graphics chips companies to deploy software-based simulation acceleration has lead us to deliver better design analysis and partitioning tools to automate the SimCluster simulation methodology," said Chilai Huang, president of Avery Design. "Automating design and SDF partitioning now brings scalable simulation performance and capacity to gate-level verification of functional and manufacturing tests, and enables critical design changes made using today's advanced timing closure process to be fully validated." The simulation analyzer is run on the original simulation database before using SimCluster to analyze a design for several critical attributes that will influence the degree of simulation acceleration. Clock recognition, event activity profiling, and interconnect analysis reports provide the key insights on potential partitioning alternatives. The auto-partitioner takes the simulation analysis (language, simulation) SIMulation ANalysis - (SIMAN) A simulation language, especially for manufacturing systems, developed by C. Dennis Pegden in 1983. ["Introduction to Simulation using SIMAN", C.D. Pegden et al, McGraw-Hill 1990]. information along with user controls and generates an augmented design netlist ready to run in SimCluster. User controls include defining hard and soft partitions, flatten and regroup re·group v. re·grouped, re·group·ing, re·groups v.tr. To arrange in a new grouping. v.intr. 1. To come back together in a tactical formation, as after a dispersal in a retreat. modes, additional clock synchronization Clock synchronization is a problem from computer science and engineering which deals with the idea that internal clocks of several computers may differ. Even when initially set accurately, real clocks will differ after some amount of time due to clock drift, caused by clocks directives, and external PLI/VPI access. The auto-partitioner can process RTL, gate, and mixed level designs. Gate-level designs can be represented as either hierarchical or flat netlists. The SDF partitioning support converts original SDF files so that they can be used with the partitioned hierarchical netlist. About SimCluster SimCluster unleashes the power of distributed computing (1) The use of multiple computers networked throughout a wide geographical area, or the world via the Internet, in order to solve a single problem. See grid computing. (2) The use of multiple computers in an enterprise rather than one centralized system. for RTL and gate-level simulation and delivers scalable simulation performance of 5-10 X speedup or more. SimCluster simulates full-chip SOCs by allocating its subsystems to multiple tightly synchronized syn·chro·nize v. syn·chro·nized, syn·chro·niz·ing, syn·chro·niz·es v.intr. 1. To occur at the same time; be simultaneous. 2. To operate in unison. v.tr. 1. simulators running on 2 or more interconnected computers. SimCluster results are fully deterministic and can be tuned for optimal performance. About Avery Design Systems Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com. |
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