Averant Joins Cadence Design Systems' Connections Program.Business Editors/High Tech Writers SUNNYVALE, Calif.--(BUSINESS WIRE)--Oct. 30, 2000 Averant, Inc., a leading provider of advanced design verification technology, today announced it is partnering with Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. through the Cadence(R) Alanza(SM) Group Connections Program. Averant will deliver an integrated verification flow that works with the Envisia(TM) Ambit (language) AMBIT - Algebraic Manipulation by Identity Translation (also claimed: "Acronym May Be Ignored Totally"). An early pattern-matching language, developed by C. Christensen of Massachusetts Computer Assocs in 1964, aimed at algebraic manipulation. (R) synthesis tool. "We are pleased to have Averant join our family of program members," said Pat Dutrow, Connections Program Director at Cadence Design Systems, Inc. "This will help broaden the wide range of solutions we can offer to our customers for a complete front-end design and verification flow." "Keeping verification on schedule is the number one bottle-neck for chip designers," commented Graham Bell Graham Bell could refer to:
About Cadence Alanza Group Connections Program Cadence provides Connections partners access to software and application notes, allowing the tightest level of interoperability between third-party software tools to be achieved. More information about the Connections Program may be obtained at www.cadence.com/thirdparty/conprogram.html. About Averant Averant, Inc., founded in 1997, is a privately held EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. company pioneering the new market for static functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, . The company provides Solidify--a design tool that delivers unprecedented performance in block-level verification for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designers. Solidify so·lid·i·fy v. so·lid·i·fied, so·lid·i·fy·ing, so·lid·i·fies v.tr. 1. To make solid, compact, or hard. 2. To make strong or united. v.intr. improves design quality, shortens design cycles, and eliminates unnecessary simulation. Averant's products are easily incorporated into synthesis and IP reuse design flows. Averant is on the web at www.averant.com, or can be reached by email at info@averant.com. Note to Editors: Solidify is a trademark of Averant, Inc. Cadence, the Cadence logo and Ambit are registered trademarks, Envisia is a trademark, and Alanza is a service mark of Cadence Design Systems, Inc. |
|
||||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion