Averant Granted Key Patent for Its Static Coverage Technology; Patent Reaffirms Averant Leadership in Static Property Verification.Business Editors/High-Tech Writers ALAMEDA, Calif.--(BUSINESS WIRE)--Aug. 6, 2003 Averant, Inc., the leader in static functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, software for Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. designs, today announced that it has been issued a new patent by the United States Patent and Trademark Office The United States Patent and Trademark Office (PTO or USPTO) is an agency in the United States Department of Commerce that provides patent protection to inventors and businesses for their inventions, and trademark registration for product and intellectual property (USPTO USPTO abbr. United States Patent and Trademark Office ) for its method of computing the design coverage of a set of properties. The method provides an easier, faster way to verify whether a circuit design works as intended, augmenting traditional circuit verification techniques, such as Verilog simulation. Averant's Solidify(TM) product allows the user to develop a set of custom properties that are verified using Averant's efficient, proprietary technology, known as static functional verification. Property verification is more exhaustive than simulation, and it does not require a testbench to specify stimuli. It is expected that property verification will have the same impact in design verification as automatic logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. had on logic design, accelerating design cycles and helping design engineers to get their products to market more quickly. A crucial question is whether the user has developed enough properties to cover all aspects of the intended behavior. Patent 6,954,804 describes how Solidify, Averant's flagship product A primary product of a company, which is typically why the company was founded and/or what made it well known. For example, MS-DOS, Windows and the Microsoft Office suite have been flagship products of Microsoft. CorelDRAW is a flagship product of Corel Corporation. , helps the user to answer this crucial question in a way that is easy to understand. As coverage analysis can be time consuming, an effort level option instructs the algorithms to trade off time for accuracy. "Several years ago, Averant was evaluating how to successfully deploy Solidify to every designer's desktop," said Mark Ross, chief technical officer of Cypress Semiconductor Corp. Ross was an early user of Solidify who advised Averant to develop an appropriate coverage technology. "A key question arose over how to judge the quality of a property set. While properties are exhaustively proven by Solidify, the design is only covered if the properties exercise all functionality of the block. Averant provides an elegant solution for the question of coverage, thereby advancing the state-of-the-art in property verification." "Developing a usable static coverage metric and algorithms used in computing it was a key turning point for property verification," said Ramin Ramin (Gonystylus) is a genus of about 30 species of hardwood trees native to southeast Asia, in Malaysia, Singapore, Indonesia, Brunei, the Philippines, and Papua New Guinea, with the highest species diversity on Borneo. Hojati, president of Averant. "In order for property verification to be a complete paradigm, one needed a suitable notion of coverage. Averant coverage technology works on the premise that if a design is functionally changed, then a complete property set should catch these design changes, i.e., some property that used to pass should fail after the changes are made. Averant's coverage technology describes how one would change the design in a representative way and how one would then compute whether the property set can catch the design changes." About Averant Averant, Inc., founded in 1997, is a privately held EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. company pioneering the new methodology and technologies for static functional verification. Averant provides Solidify(TM), a design tool that delivers unprecedented performance in block-level verification for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designs. It is a high-capacity, static RTL analysis tool that verifies the functional behavior of Verilog or VHDL blocks without using simulators or test vectors. Solidify improves design quality, reduces risk and uncertainty, shortens design cycles, and reduces the need for simulation based verification. Averant's products are easily incorporated into synthesis, IP reuse, and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. design flows. Averant is on the Web at www.averant.com, or can reached by email at info@averant.com. |
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