Averant Announces a Significant Update to Solidify.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--March 20, 2003

Averant Releases Solidify 2.8, Introducing Enhanced Property

Language, Enhanced and Expanded Automatic Static Checks, Increased

Capacity, and Improved Usability

Solidify(TM) 2.8 includes

-- Second generation auto cone reduction technology

-- Significant enhancement to HPL including clock sensitivity, sequencing operators, past tense operators, and monitors

-- Expanded auto checks, including array over-bound for Verilog, and VHDL deadcode check

-- Increased capacity with auto checks running fully statically on multi-million gate designs

-- Improved support for OVL verification

-- Partitioned auto checks for faster turn-around time

-- Improved hierarchical verification path

-- Numerous refinements based on user feedback from over 25 customer companies

Averant, Inc., the leader in static functional verification software for RTL level Verilog and VHDL designs, today announced the release of Solidify 2.8.

Averant's property description language, HPL, allows design and verification engineers to easily express properties of their designs. In 2.8, HPL has been significantly enhanced. Specifically, the users can now more easily express complex patterns, create monitors, attach clock sensitivity list to properties, and use past tense operators. These features better position Solidify for IP verification and integration tasks, including packaged bus verification.

Automatic cone reduction allows users to quickly verify a modified version of the property, usually equivalent to an astronomical number of test vectors. Solidify 2.6 introduced this technology. In release 2.8, this capability has been enhanced to better ensure the modified property captures the essence of the original property.

Solidify continues to aggressively improve the included automatic checks. In 2.8, partitioning of the checks were introduced which allows a user to run the checks on a set of machines, and hence, increase the turn-around time for getting results. Solidify is now able to run auto checks on multi-million gate designs flat, and fully statically. New capabilities such as array over bound for Verilog and dead code check for VHDL are also included in this release. Previously provided features such as dead code for Verilog have also been extensively renovated.

Hierarchical verification allows users to verify failing properties of a module at high levels of the hierarchy. If a property passes at a higher level, one knows the failure at the lower levels was due to inadequate specifications of assumptions at the lower levels. Solidify 2.8 enhances the ease of use of Solidify's hierarchical verification capability.

Open Verification Library (OVL) is a library of assertions, allowing simple assertions to be instantiated inside the RTL. Solidify first supported static verification of OVL properties in 2.6. In 2.8, this support has been significantly enhanced.

The feedback from our user base of over 25 leading companies around the globe has resulted in a number of smaller refinements to Solidify. These are reflected in the verification engine, GUI, hierarchical verification, HPL, property language, and language compilers.

Availability

Solidify 2.8 will be available on CD-ROM or FTP at the beginning of April 2003, and may be requested by email at [e-mail]. Solidify 2.8 will be sent to all Solidify customers that subscribe to maintenance. Solidify is available for PCs running Windows 95/98/NT4.0/2000 or Linux Red Hat 6.2 or later, and for workstations running Sun Solaris 2.6/2.7/2.8.

About Averant

Averant, Inc., founded in 1997, is a privately held EDA company pioneering the new methodology and technologies for static functional verification. Averant provides Solidify(TM), a design tool that delivers unprecedented performance in block-level verification for RTL designs. It is a high-capacity, static RTL analysis tool that verifies the functional behavior of Verilog or VHDL blocks without using simulators or test vectors. Solidify improves design quality, reduces risk and uncertainty, shortens design cycles, and reduces the need for simulation based verification. Averant's products are easily incorporated into synthesis, IP reuse, and FPGA design flows. Averant is on the web at www.averant.com, or can reached by email at [e-mail].