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Averant Announces Release of Solidify(TM) 5.0.


HAYWARD, Calif. -- Averant Inc., a leading provider of advanced verification technology for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences;  designs, today announces the release of Solidify 5.0, continuing its First In Formal[TM] leadership in formal property verification. The key new features of the tool - three of which are industry firsts - significantly expand upon Solidify's capabilities:

* Guided Proof System (GPS) 2.0. Averant first introduced its breakthrough GPS technology with Solidify 4.0. GPS 2.0 adds verification management and hierarchical verification (an industry first).
        -- Verification management keeps track of the results of
           previous runs, so that when a property passes GPS does not
           need to reverify the property unless the RTL has changed.

        -- When properties are proved for a given block, assumptions
           have usually been made regarding the legal inputs to the
           block. Automated hierarchical verification enables the user
           to prove properties at one level of hierarchy, then go to
           the next level up in the hierarchy, and prove that both the
           properties already proven and the assumptions made at the
           lower level still hold. This allows much more rigor in the
           verification methodology.


* Coverage Expansion (industry first). Solidify 5.0 introduces the CE Engine. The CE Engine includes an innovative technique for testbench-less bug hunting with formal engines. As the CE Engine goes through its iterations, it reports the additional coverage achieved by Solidify. The CE Engine also supports VCD See Video CD.

VCD - Video Compact Disc
 files as inputs to set the starting state for Solidify, allowing bug hunting from a potentially interesting point in the operation of the design.

* isunknown support in SVA SVA School of Visual Arts
SVA Severe (Thunderstorm) Advisory
SVA Statens Veterinärmedicinska Anstalt (National Veterinary Institute, Sweden)
SVA Shareholder Value Added
, PSL 1. PSL - Portable Standard Lisp.
2. PSL - Problem Statement Language. See PSL/PSA.
 and HPL HPL - Language used in HP9825A/S/T "Desktop Calculators", 1978(?) and ported to the early Series 200 family (9826 and 9836, 68000). Fairly simple and standard, but with extensive I/O support for data acquisition and control (BCD, Serial, 16 bit custom and IEEE 488 interfaces), . Solidify is now the first property checker to support the isunknown construct in SVA, PSL and HPL, for full three-state formal verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 of properties.

* Engine improvements for partial pass reduction. Solidify 5.0 introduces a set of new techniques to reduce the number of partially passed properties, and increase the number of fully proven properties. These technologies work in conjunction with the CE Engine, providing for more of the verification work to be done using formal verification, thus improving verification productivity.

* Multi-core operation. Solidify can take advantage of multiple CPU CPU
 in full central processing unit

Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit.
 workstations, distributing property verification over the multiple processors for a nearly linear speedup in runtime.

"Solidify 5.0 sets a new standard in static functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, ," commented Ramin Ramin (Gonystylus) is a genus of about 30 species of hardwood trees native to southeast Asia, in Malaysia, Singapore, Indonesia, Brunei, the Philippines, and Papua New Guinea, with the highest species diversity on Borneo.  Hojati, president of Averant. "Taken as a group, these improvements enable Solidify's users to focus on verification, and not on learning how to run a formal verification tool. Solidify 5.0 allows customers to prove more properties, find more bugs and accelerate verification closure for their projects."

Availability

Solidify 5.0 will be available in July on Linux (32 and 64 bit), Windows and Solaris platforms.

About Averant

Averant Inc., founded in 1997, is a privately held EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  firm pioneering new methodology and technologies for static formal verification. Averant's flagship product is Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks - all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at http://www.averant.com.
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Copyright 2007, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Date:May 31, 2007
Words:532
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