Averant Announces Release of Solidify, Version 3.1.ALAMEDA, Calif. -- Averant Inc., a leading provider of advanced verification technology for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designs, today announces the release of Solidify 3.1, providing extensive enhancements to performance and usability. Averant raises the ante once again with its latest version of Solidify, the most complete, battle-hardened and field-proven tool in its class. Highlights of the new release include: --Improved PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. flow --Initial support for the SVA SVA School of Visual Arts SVA Severe (Thunderstorm) Advisory SVA Statens Veterinärmedicinska Anstalt (National Veterinary Institute, Sweden) SVA Shareholder Value Added language --Improvements to the engine and HPL HPL - Language used in HP9825A/S/T "Desktop Calculators", 1978(?) and ported to the early Series 200 family (9826 and 9836, 68000). Fairly simple and standard, but with extensive I/O support for data acquisition and control (BCD, Serial, 16 bit custom and IEEE 488 interfaces), , Averant's property specification language --Complete rewrite of the command shell and graphical user interface graphical user interface (GUI) Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to in C --Streamlined project manager for organizing and managing design projects --Enhancements to the automatic checking capability, including extended FSM error detection --Improved hierarchical verification --Improved source code debugging "Solidify is the industry's premier property verification tool including very fast and comprehensive engines, patented coverage technology, patent-pending memory modeling, support for full block-level property verification, support for formal assertion-based verification, best-in-class automatic checks, best-in-class protocol verification, support for many assertion languages, industry leading property linting, and built-in source code debugging," offered Dr. Ramin Ramin (Gonystylus) is a genus of about 30 species of hardwood trees native to southeast Asia, in Malaysia, Singapore, Indonesia, Brunei, the Philippines, and Papua New Guinea, with the highest species diversity on Borneo. Hojati, president of Averant. "Release 3.1 is the culmination of numerous improvements, extending Averant's lead in this market." Pricing and Availability Solidify 3.1 is available immediately and may be downloaded or purchased on CD-ROM CD-ROM: see compact disc. CD-ROM in full compact disc read-only memory Type of computer storage medium that is read optically (e.g., by a laser). . Platform support includes Windows NT4.0/2000/XP or Linux Red Hat 7.2 or later, and workstations running Sun Solaris 2.6/2.7/2.8. Solidify, which includes Verilog or VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. input, property verification in HPL and OVL, and auto checks, is priced at $40,000. The coverage option is priced at $20,000. Mixed Verilog-VHDL support, PSL and SVA are options each priced at $10,000. All pricing is for one floating perpetual license with maintenance being 20% of the list price in the US market. About Averant Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averant provides Solidify(TM) a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks -- all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our Web site at http://www.averant.com. |
|
||||||||||||||

Printer friendly
Cite/link
Email
Feedback
Reader Opinion