Averant Announces Release of Solidify(TM) 4.0.

HAYWARD, Calif. -- Averant Inc., a leading provider of advanced verification technology for RTL designs, today announces the release of Solidify 4.0, continuing its First In Formal(TM) leadership in formal property verification. The key new features of the tool -- two of which are industry firsts -- significantly expand upon Solidify's capabilities:

--Guided Proof System (GPS). Solidify is the first formal tool to give users fine control over proofs to achieve the best use of computational resources. For example, early in the design cycle during bug hunting, the user may need to process 100 properties in seconds on a single computer. Later, when the focus shifts to exhaustive proofs, the user may have days and several machines to process these properties. By trading off completeness and accuracy against CPU time, Solidify can provide valuable early feedback, while achieving maximum use of available compute power.

--Robust SVA support. As the SystemVerilog language becomes more widely utilized by the design community, the SystemVerilog Assertion (SVA) portion of the language is leading the charge in user adoption. Now, in Solidify 4.0, the entire SVA language is supported. Also supported is the use of inline SVA, verification IP attached through the bind command, and the Open Verilog Library (OVL) implemented in SVA.

--Universal property language compilers. Another industry first -- Solidify introduces the ability to translate between several property languages including SVA, PSL, OVA, OVL and HPL. This gives design teams complete freedom to choose the property language that best serves their needs, and allows easy preservation and reuse of valuable verification IP.

Other enhancements to Solidify 4.0 include:

--Extended debugging capabilities. The debug trace facility has been enhanced with native waveform viewing, more flexible signal selection, search capabilities, and improved testbench generation. This results in improved debug productivity and better integration with simulators.

--Extended clock crossing checks. Data stability, gray-code and crossing protocol checks have been added to list of crossing check.

--PSL version 1.1 now supported.

--Mixed Verilog95, Verilog2K, SystemVerilog. Solidify now handles any mix of Verilog descriptions in the same design. This helps preserve legacy IP, allowing it to be used unchanged together with modules that rely on newer language features.

--Support of Liberty gate-level format. To improve support of gate-level designs, Solidify now supports Liberty's cell format.

"This list represents a comprehensive series of improvements to the tool, and combines input from some of the best CAD, verification, and design engineers on the globe," commented Ramin Hojati, president of Averant. "With this new release, leading edge design teams have the tools to tackle the most demanding verification challenges. Solidify 4.0 should set a new standard in our industry."

Availability

Solidify 4.0 will be available in August on Linux, Windows and Solaris platforms.

About Averant

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averant provides Solidify(TM), a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks -- all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our Web site at http://www.averant.com.