Averant Announces New Engine, Next Generation Testbench-less Bug Hunting, Support for System Verilog.HAYWARD, Calif. -- Averant Inc., a leading provider of advanced verification technology for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designs, today announces the development of significant new technologies, continuing its First In Formal[TM] leadership in formal property verification. * New Verification Engine. Maximizing the number of conclusive passes remains a goal of formal verification
In the context of hardware and software systems, formal verification . Averant has developed a new engine based on proprietary algorithms capable of proving some previously unproven properties. This engine is seamlessly integrated in Averant's guided-proof system environment. * Next Generation Testbench-less Bug Hunting. To find deep bugs, Averant pioneered testbench-less bug hunting last year. Next generation testbench-less bug hunting improves the quality and speed of first generation algorithms, reaching more of the design space in significantly less time. * System Verilog Design Support. System Verilog Design (SVD (Simultaneous Voice and Data) The concurrent transmission of voice and data by modem over a single analog telephone line. The first SVD technologies on the market were Multi-Tech's MSP, Radish's VoiceView, AT&T's VoiceSpan and the all-digital DSVD, endorsed by ) constructs support higher level specification of designs, and may become more widely used in the future. "Averant's engines have been the leaders in the industry for many years now," commented Ramin Ramin (Gonystylus) is a genus of about 30 species of hardwood trees native to southeast Asia, in Malaysia, Singapore, Indonesia, Brunei, the Philippines, and Papua New Guinea, with the highest species diversity on Borneo. Hojati, president of Averant. "We continue to build on our strength while improving usability and design flow support." Availability The new engine is available now. Most of SVD constructs are available now, with the rest becoming available over the summer. Much of next generation bug hunting is available now, but some features will be coming later in the summer. About Averant Averant Inc., founded in 1997, is a privately held EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. firm pioneering new methodology and technologies for static formal verification. Averant's flagship product A primary product of a company, which is typically why the company was founded and/or what made it well known. For example, MS-DOS, Windows and the Microsoft Office suite have been flagship products of Microsoft. CorelDRAW is a flagship product of Corel Corporation. is Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks - all without the need for simulators or test vectors The introduction to this article provides insufficient context for those unfamiliar with the subject matter. Please help [ improve the introduction] to meet Wikipedia's layout standards. You can discuss the issue on the talk page. . These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at http://www.averant.com. |
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