Avant! Expands IC/ASIC Logic Design Business

New Methodology Dramatically Shortens Time-to-Market by Achieving Single Pass

                              Timing Convergence

FREMONT, Calif., June 09 /PRNewswire/ -- Avant! Corporation (Nasdaq: AVNT) today announced SinglePass(TM), a new methodology that allows designers to achieve single-pass timing convergence, resulting in dramatically shorter time to market for very deep submicron (VDSM) designs at 0.25u and below.

"Our customers are missing critical market opportunities because their design times are too long," said Chi-Ping Hsu, Ph.D., CEO Staff for Products at Avant!. "It is no longer possible to separate the logic, timing, and layout optimizations for performance-critical VDSM designs. Avant!'s new SinglePass methodology not only eliminates time consuming frontend and backend iterations, but also generates higher performance designs that existing methodologies cannot achieve," continued Chi-Ping Hsu.

"Larger chips and faster clock frequencies translate into a need to use actual layout information in the design process," commented Kenny Rice, Imaging Systems Division, Consumer Systems Group of Motorola. "We believe Avant!'s new methodology will allow us to achieve faster time to market and higher design performance."

Limitations of Conventional Methodology

The greatest challenge facing VDSM designers today is overcoming the inability of logic synthesis to predict the effects of layout on chip-level timing at geometries of 0.25u and below. This limitation is due to the ineffectiveness of logic synthesis tools to model interconnect delay and parasitic effects of the actual layout.

Interconnect delays now account for up to 70% of total timing delay in advanced multi-million gate designs. At this time it is not possible to synthesize an entire million-gate design at one time, therefore, the design must be partitioned into smaller blocks and timing specifications must be estimated for each block. Consequently, logic synthesis cannot optimize global critical paths.

Floorplanning was introduced to more accurately estimate delays for each block and also model inter-block delay. Although standalone floorplanning gives users a better estimate of global critical paths and block interconnect delay, the technology still cannot estimate layout delays accurately enough to avoid multiple iterations though the synthesis/layout loop.

The number of iterations created by standalone floorplanning makes it difficult to meet timing specifications. In fact, designs have been canceled because the timing correlation between synthesis and layout diverges after more than 15 iterations through the design loop. Customers using Avant!'s single-pass methodology and products can eliminate iterations caused by this synthesis inaccuracy and get their designs to market faster. This methodology brings layout into the logic design process and makes it possible for customers to achieve a higher level of performance in their designs, enabling them to differentiate their products in the marketplace.

Components of the New Methodology

The SinglePass methodology combines simultaneous logic, layout, and timing optimization with accurate layout information. Designers presently use Planet RTL for register transfer level (RTL) design floorplanning to analyze timing, create custom wire load models and block-level timing budgets for single-pass synthesis based on an accurate floorplan. RTL floorplans identify block placement, inter-block routing and estimated cell placements. After logic synthesis, designers use Apollo to perform timing driven layout on each block, then run Saturn to do further layout and logic optimization to improve block and chip timing. When the block is completed, the actual delays and size can be read back into Planet RTL for chip re-timing. Designers can then refine the timing budget and begin the next block or update designers of other blocks.

Planet, Apollo, and Saturn all share the same environment and read design data directly from the Milkyway common database, thereby accelerating turnaround time by avoiding the long read times and large files associated with independent tools. As Planet has incremental operation and can directly read the Milkyway database, designers use actual completed blocks to further refine their timing budgets for the next block to be designed. Planet, Apollo, and Saturn also use the same timing analyzer, extraction, and delay calculator, thus assuring uniform timing accuracy and consistency through the design process.

A preview of the SinglePass methodology will be available at the Design Automation Conference (DAC), to be held in San Francisco June 15-18.

About Avant!

Avant! (pronounced ah VANH tee) Corporation develops, markets, and supports integrated circuit design automation (ICDA) software for the simulation, layout, verification and analysis of deep submicron ICs including microprocessors, microcontrollers, application-specific standard products (ASSPs) and complex application-specific integrated circuits (ASICs). The company is headquartered in Fremont, California with offices located worldwide.

Tel: [phone], Fax: [phone]. www.avanticorp.com.

NOTE: Avant! Apollo, Milkway, Planet, Planet RTL, SinglePass, and Saturn are trademarks of Avant! Corporation. All other company and product names mentioned herein are trademarks or registered trademarks of their respective owners and should be treated as such.

SOURCE Avanti! Corporation

    -0-                             06/09/98

/CONTACT: Greg Fawcett, Public Relations, 510-413-8022, or [e-mail], or Chi-Ping Hsu, Products and Technology, 510-413-8000, or [e-mail], both of Avant!/

/Company News On-Call: http://www.prnewswire.com or fax, 800-758-5804, ext. 117514/

/Web site: http://www.avanticorp.com/

(AVNT)

CO: Avanti! Corporation ST: California IN: CPR SU: ERN PDT 

DM-CS -- SFTU018 -- 1650 06/09/98 06:30 EDT http://www.prnewswire.com