Avant! Announces New Register Transfer Level Floorplanning Technology for DSM IC Design Automation; Planet-RTL Technology Predicts and Optimizes Cycle Time, Die Size and Power for Deep-Submicron Design in RTL Phase of Development Cycle.

SUNNYVALE, Calif.--(BUSINESS WIRE)--Feb. 10, 1997--Avant! Corporation (Nasdaq: AVNT) today announced its new register transfer level (RTL) floorplanning technology, Planet-RTL(TM). This new technology will allow IC designers to predict chip performance and size prior to the synthesis process helping to meet critical engineering constraints such as performance, design size and power and consequently improve product time-to-market.

The complex physical requirements of deep-submicron (DSM) IC designs (feature sizes 0.5-micron and below) have put a premium on supplying designers with quick and honest feedback during the RTL design cycle to improve their confidence at the earliest stages of IC development. The ability to accurately predict physical behavior is the key to successful RTL floorplanning. Avant!'s new technology will let designers estimate design structure and area based on RTL descriptions and perform early exploration of possible physical implementation to get early feedback and allow them to make design adjustments concurrently.

"Based on Avant!'s experience, we believe that a good RTL floorplanning tool should share common algorithms with an industry-proven place and route system. Existing commercial RTL floorplanners are either implemented with home-grown and unproven place and route algorithms, or integrated with other place and route technologies through often risky translations. These point solution tools frequently create more headaches than benefits to designers of DSM ICs.

Planet-RTL, which will be released in May, is Avant!'s newest technology built around our industry-leading Aquarius-XO(TM) place and route tool. Planet-RTL will provide IC developers with reliable predictions of physical behavior resulting in accurate design constraint data earlier in the design cycle. Without the assistance of dependable tools like Planet-RTL early in the development cycle, future DSM IC design will become a virtual `mission impossible,'" said Y.Z. Liao, vice president of layout products division at Avant!.

Planet-RTL Technology Detail

Planet-RTL will provide users with block size and block structure estimation from Verilog HDL description and timing budgeting based on the actual placement of blocks. In addition, users will be able to automatically generate multiple block placements based on user-specified constraints, allowing designers to explore multiple front-end floorplans for optimal timing performance.

Timing budgeting capability will create timing budgets for each module after inter-module and intra-module connections are estimated, providing accurate boundary constraints for each RTL module. This will allow designers to perform synthesis fine tuning to guarantee accurate timing and power. If a module has been synthesized, its area can be more accurately estimated by a fast placer within Planet that will give more accurate area, timing and wire-load model reports.

Future chip designs laid out by Aquarius will have more than 100K synthesized gates per RTL module. The traditional RTL design approach is to use one default wire-load model for all blocks without predicting actual placement of the blocks. RTL designs hide design problems until the first few attempts of physical layout, causing hard-to-fix problems, in addition to causing a measurable productivity loss. This is no longer acceptable for deep-submicron designs because interconnect delays dominate the total delays. Planet-RTL will help give realistic feedback early and automatically generating synthesis constraint scripts to help designers easily make early design adjustments.

Avant! released its Version 2.1 floorplanning tool in December 1996. This version includes automatic timing budgeting and the same timing analysis engine as in all timing-driven applications of Avant!'s Aquarius place and route tools. In Version 2.1, timing budgeting results can be saved in a user-modifiable text file. Users are now also able to translate V2.1 budgeting results to Synopsys Design Compiler scripts. May's release of Planet-RTL will also add block area estimation from unsynthesized Verilog RTL module descriptions.

About Avant!

Avant! (pronounced ah VANH tee) Corporation develops, markets, and supports integrated circuit design automation (ICDA) software for the layout, verification and analysis of deep-submicron ICs including microprocessors, microcontrollers, application-specific standard products (ASSPs) and complex application-specific integrated circuits (ASICs). The company is headquartered in Sunnyvale, California. Telephone: [phone]. Fax: [phone]. Worldwide Web: http://www.avanticorp.com . -0-

NOTE TO EDITORS: Planet-RTL and Aquarius-XO are trademarks of Avant! Corporation. All other company and product names are trademarks or registered trademarks of their respective owners and should be treated as such.

CONTACT: Avant!

Don Davis, 408/523-8911

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Vic Kulkarni, 408/328-8681

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