Avant! Announces New IC Design Technology to Calculate and Analyze Chip Performance.

SUNNYVALE, Calif.--(BUSINESS WIRE)--May 6, 1996--Avant! Corporation (Nasdaq:AVNT), the leader in deep submicron technology, today announced a new integrated circuit design automation (ICDA) product called Star that analyzes the performance of deep submicron ICs, including the most complex, high-performance microprocessors. The results from Star analysis provide critical information to designers so they can produce ICs that are smaller and faster and consume less power.

Star is a full-chip extraction, delay calculation, and data reduction tool for IC designers to use during physical design, the most critical phase of IC design. Star is tightly integrated with Avant!'s hierarchical layout and verification tools, ArcCell and VeriCheck, providing the most efficient, accurate and predictable performance possible for high-speed designs.

Star calculates or "extracts" designed devices, such as transistors and diodes, and extracts the resistance and capacitance (RC) values (called "parasitics") of the wires connecting the devices ("interconnect"). This new product also accurately calculates the logic and interconnect delays for the entire chip.

Star's Smart Extraction capability takes the guesswork out of extraction. Its proprietary simulation and analysis algorithms automatically determine and apply the correct level of extraction accuracy needed for each net in the design. Star produces the smallest possible extracted circuit with the accuracy of an exhaustive full-chip RC extraction.

Hideyuki Kikuchihara, manager of the VLSI Design Methodology Section of Oki Electric Industry Co. (Tokyo, Japan), understands from experience the challenges of physical design for deep submicron ICs. "Because the parasitics dominate the overall design performance, the design of deep submicron circuits is fully dependent on the accuracy of the extraction tools used." Oki sought a new extraction solution because their existing design tools did not achieve the accuracy or turn-around time needed for their deep submicron designs.

Kikuchihara added, "With Avant!'s products, especially the Smart Extraction capabilities of Star, we are able to accomplish full chip extraction with the high accuracy Oki needs to produce our deep submicron ICs. We believe that using Star for extraction of our high-end ASIC designs will help us achieve our objectives: accuracy approaching that of 3-D device simulators, reasonable extraction file sizes, and practical turnaround times."

Input/Output

Star supports input of GDSII and CIF layout data and output of SPICE and SPF circuit netlists, and SDF for delay information. For delay calculation Star supports k-factor and table models as well as Synopsys, Pearl, and Verilog models.

Price and Availability

Star, which includes Smart Extraction, data reduction, delay calculation, and a TCAD (technology CAD) interface, will be demonstrated at the Design Automation Conference in Las Vegas, Nevada, June 3-6. It is available immediately on DEC Alpha, HP 700, IBM RS6000, Silicon Graphics, and Sun platforms. A graphical delay analysis tool for Star will be available in the third quarter of this year. U.S. pricing begins at $125,000.

Background Information on Extraction

The contribution of a design's interconnect delay to the total delay of the design has become too important to ignore without the risk of manufacturing an IC that does not meet its performance requirements. One approach to ensure that a design meets its performance requirements is to use conservative delay estimates. However, this results in over-designed, lower-performance ICs which are larger, require more silicon, and consume more power than is necessary.

To prevent over-design, conservative estimates must be replaced with accurate delays calculated from RC data extracted from the design. Avant!'s Star uses proprietary enhancements to the Asymptotic Waveform Evaluation (AWE) and Effective Capacitance (Ceffective) techniques to provide accurate delay values.

Existing extraction tools do not provide the level of accuracy and performance needed to verify multi-million-transistor designs. Therefore, designers have to guess where to apply accurate, detailed extraction. While the overall extraction run times may be acceptable, designers may miss critical areas that are needed to properly verify the design. Designers cannot apply detailed extraction to the whole chip, as run-times are either unacceptable or infinite, and the volume of data produced is too large to be analyzed by timing tools or circuit simulators such as SPICE.

Avant! Corporation develops, markets and supports integrated circuit design automation (ICDA) software for deep submicron ICs, microprocessors, microcontrollers, application-specific standard products (ASSPs) and complex application-specific integrated circuits (ASICs). Company headquarters are located in Sunnyvale, California, telephone [phone]. World Wide Web site: http://www.avanticorp.com. -0-

Note to Editors: Star and Smart Extraction are trademarks and ArcCell and VeriCheck are registered trademarks of Avant! Corporation. All other names are the property of their respective holders and should be treated as such.

CONTACT: Avant! Corporation

Lois DuBois, 408/523-8857 or 408/738-8881