Avant! Acquires Formal Verification Firm Chrysalis.
North Billerica, Massachusetts-based Chrysalis owns a 64% share of the verification market with its Design Verifyer equivalence checking and Design Insight Model Setting tools, according to Dataquest figures. Around 100 companies use the tools, including Advanced Micro Devices Inc, LM Ericsson AB, Fujitsu Ltd, Hewlett-Packard Co, IBM Corp, LSI Logic Inc, Sun Microsystems Inc and Texas Instruments Inc. Avant! plans to integrate the technology into its SinglePass design software, which combines logical and physical design.
All the mainstream electronic design automation companies have been moving verification technologies into their mainstream systems, mostly through acquisition. Cadence Design Systems Inc launched its first verification tools in May 1998, and later in the year acquired the Bell Labs Design Automation unit from Lucent Technologies Inc. Earlier this year it acquired another verification firm, Design Acceleration Inc. And Cadence also acquired hardware based design emulation and verification company Quickturn Systems Inc this year, after a long battle with Mentor Graphics Corp. Mentor bought OPC Technology Inc in November last year. Synopsys launched its Formality tool in February 1998, and supplemented its existing Epic and Viewlogic acquisitions by buying verification company Systems Science Inc. IBM Corp also has its own formal verification department in Haifa, Israel, and its own Rulebase product line.
Small companies, however, have found it hard to put in the huge investments required to develop complex semiconductor design testing tools. Chrysalis' most direct competitor, Abstract Inc, failed last year despite a cash injection from Intel Corp. Other small companies still in the market include Fremont, California-based Verysys Electronic Design Automation Inc, Formalized Design, Inc of Chandler, Arizona, and Verplex Systems, Inc, a Santa Clara, California-based start-up.
The market is being driven by the new interest in systems-on-a-chip technology, which is leading to a "design gap" between the design process, now easily capable of fabricating parts with tens of millions of gates, and the verification process, which cannot cope with such huge numbers, so that mathematical testing methods are necessarily replacing the old methods of gate level simulation. Research has shown that there are already four to five engineers working on design verification to every one working on the design itself.
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|Date:||May 6, 1999|
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