Atrica Selects Lattice 10 Gigabit Ethernet Field Programmable System Chips -- FPSCs -- For Carrier-Class Metro Core Switches.Business Editors/High-Tech Writers HILLSBORO, Ore.--(BUSINESS WIRE)--Feb. 24, 2003 Lattice Semiconductor Corporation (Nasdaq:LSCC LSCC Lake-Sumter Community College (Florida) LSCC Lattice Semiconductor Corporation (stock symbol) LSCC Lawson State Community College (Alabama) ) today announced that Atrica has selected Lattice's ORLI10G product, a programmable 10 Gigabit Ethernet line interface chip, for use in Atrica's A-8000 family of Optical Ethernet core switches. The A-8000 family, including the A-8800 and A-8100, are high-performance metro core switches designed to scale from 10 Gigabit Ethernet to 320 Gbps with fully integrated optical switching. Recently, Atrica announced that France Telecom chose the Atrica Optical Ethernet system for deployment of metro services in the Paris region. The Ethernet services announced by France Telecom include high bandwidth Internet access, Ethernet leased lines and Transparent LAN Services. Lattice's ORLI10G line interface device is a Field Programmable System Chip (FPSC FPSC Florida Public Service Commission FPSC Financial Planners Standards Council (Canada) FPSC Field Programmable System Chip (Lucent Technologies) FPSC Fundación Promoción Social de la Cultura ) that provides data networking equipment designers with customizable, protocol-independent interfaces to high-speed optical transport facilities used in Local Area Network (LAN (Local Area Network) A communications network that serves users within a confined geographical area. The "clients" are the user's workstations typically running Windows, although Mac and Linux clients are also used. ), Wide Area Network (WAN), and Metro Area Network (MAN) deployments. The chip implements a 10 Gigabit Sixteen Bit Interface (XSBI XSBI 10 Gigabit Sixteen-Bit Interface (IEEE 802.3) XSBI Ten Gbps Sixteen Bit Interface ) for optical transponders (modules that combine optical transmitters and receivers with associated electronics) in efficient standard cell logic, as well as a 10 Gigabit Media Independent Interface (XGMII XGMII 10 Gbit Media Independent Interface XGMII Ten Gbps Media Independent Interface ) for 10 Gigabit Ethernet Media Access Control (MAC) circuits in programmable logic. The XGMII interface is a key part of Lattice's Physical Coding Sublayer The Physical Coding Sublayer (PCS) further helps to define physical layer specifications for ethernet. The Ethernet PCS sublayer is part of the Ethernet PHY layer. The hierarchy is as follows: (PCS (1) (Personal Communications Services) Refers to wireless services that emerged after the U.S. government auctioned commercial licenses in 1994 and 1995. This radio spectrum in the 1. ) Intellectual Property core. The ORLI10G employs Lattice's ORCA(R) Series 4 field-programmable gate array (hardware) field-programmable gate array - (FPGA) A gate array where the logic network can be programmed into the device after its manufacture. An FPGA consists of an array of logic elements, either gates or lookup table RAMs, flip-flops and programmable interconnect wiring. (FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. ) architecture which is specifically designed to accommodate networking Intellectual Property (IP) cores. "Our customer successes with the A-8800 core switch validates Atrica's vision of delivering carrier-class Ethernet solutions at enterprise Ethernet prices," said Tim Dixon, Atrica vice president of marketing. "Lattice's Field Programmable System Chip approach has helped us bring this solution to market by providing a fully functional interface between optical components and today's 10 Gigabit Ethernet MAC implementations, yet one we can easily reprogram in the future to comply with new customer requirements." "Atrica's innovative Optical Ethernet solution that integrates Ethernet with traditional SONET services is an ideal application for Lattice's programmable networking system-chip technology," said Stan Kopec, vice president of marketing at Lattice Semiconductor. "By utilizing our high speed standard cell macros, field programmable gate array See FPGA. logic and flexible networking IP cores, system developers like Atrica can move forward knowing that changes to communications standards won't impose time-consuming delays as they get their products to market." Additional A-8800 / A-8100 Metro Core Switch Information The A-8100 is a 17-slot, high-density, one-third rack chassis that supports up to 15, 10-Gigabit Ethernet ports, or up to 120 Gigabit Ethernet ports. It features 150 Gbps non-blocking switching and boasts up to 450 million packets per second in provisioned throughput. The A-8100 employs a standard MPLS-based architecture to deliver scalable flow management. It also features sub-50 millisecond failure recovery, redundant DC power and full redundancy of all common equipment. The A-8100 is an ideal Metro aggregation switch, delivering scalable, high-density Gigabit Ethernet and 10 Gigabit Ethernet performance. The A-8800 is a 34-slot, high-density chassis that integrates the industry's highest capacity integrated Ethernet and wavelength switching capabilities, delivering unmatched scalability for Metro cores. The A-8800 features 10 Gigabit Ethernet interfaces and a standard MPLS-based architecture that is capable of engineering up to 500,000 flows. Hot swappable module support includes redundant switch management, Gigabit Ethernet, 10 Gigabit Ethernet and DWDM (Dense WDM) The term given to wavelength division multiplexing (WDM) when significantly more channels were being added. Since WDM is increasingly more "dense" all the time, both terms are used synonymously. See WDM. DWDM - wavelength division multiplexing . The A-8800 multiplexes up to 32 wavelengths of 10 Gigabit Ethernet on a single fiber, adding and dropping any wavelength at any node. The A-8800 also offers full protection with sub-50 millisecond failure recovery as well as redundant DC power and full redundancy of all common equipment. Additional ORLI10G Technical Information Lattice's ORLI10G implements forward clocked, 16-bit transmit and receive 10 Gbit/s interfaces (as per OIF 99.102.5). This 16-bit interface runs at the following rates: -- 622 Mbits/s: OC-192/STM-64 SONET/SDN interface (SFI-4) -- 645 Mbits/s: 10 Gigabit/s Sixteen-bit Interface (XSBI) -- 667 Mbits/s: Strong FEC interface (digital wrapper and OC-192/STM-64) -- 781 Mbits/s: Super FEC interface (digital wrapper and OC-192/STM-64) -- 850 Mbits/s: Super FEC interface (digital wrapper and OC-192/STM-64) The device interfaces directly to industry-standard multiplexer and demultiplexer ICs. This allows Lattice to offer cost-effective solutions for a variety of line interfaces: -- Optical Internetworking Forum The Optical Internetworking Forum (OIF) was organized to facilitate and accelerate the development of next-generation optical internetworking products. The OIF produces Electrical, Tunable Laser, Very Short Reach Hardware Interfaces. (OIF) SERDES See serializer/deserializer. - Framer Interface (SFI-4) -- 10 Gigabit Ethernet 16-bit Interface (XSBI) -- 10 Gbit/s Strong Forward Error Correction A communications technique that can correct bad data on the receiving end. Before transmission, the data are processed through an algorithm that adds extra bits for error correction. If the transmitted message is received in error, the correction bits are used to repair it. (FEC) rates -- 12.5 Gbit/s Super FEC rates Lattice's 10 Gigabit Ethernet PCS (Physical Coding Sublayer) intellectual property core includes the following features: -- Elastic buffers implemented as 256x72 FIFOs in embedded RAM -- XGMII for interfacing to 10 Gbits/s Ethernet MACs -- 64/66b encoder/decoder -- Scrambler A device or software program that encrypts data for security purposes. See scramble. and deScrambler de·scram·bler n. An electronic device that decodes a scrambled transmission into a signal that is intelligible to the receiving apparatus. descrambler with word aligner (x59 + x39 +1) -- Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s SONET/SDH MUX/deMUX functions -- Idle insertion and deletion -- Serial Management Interface (SMI) compliant with Clause 45 of the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 802.3ae standard Lattice can deliver the PCS core as a ready-to-run bitstream or with VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. source code along with simulation and synthesis scripts and complete documentation. About Atrica Atrica's mission is to deliver the most cost-effective, high-performance Optical Ethernet platforms to forward-thinking service providers who are building next-generation Metro networks today. Atrica is a privately held company privately held company A firm whose shares are held within a relatively small circle of owners and are not traded publicly. based in Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. , with R&D facilities in Israel and business development and sales offices throughout Europe and Asia Pacific. The company has received a total of $117 million in funding to date, including seed funding from 3Com Corporation, first round financing from prominent Silicon Valley venture funds Accel Partners and Benchmark Capital, second round financing from five leading global service providers and a third round led by St. Paul Venture Capital. For more information, visit Atrica on the Web at www.atrica.com. About Lattice Semiconductor Corporation Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGAs), Field Programmable System Chips (FPSCs) and high-performance ISP(TM) programmable logic devices (PLDs). Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ISP, ORCA and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. |
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