Atrenta Introduces PeriScope, an Automated Functional Analysis Product, to Slash Verification Time.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--June 1, 2004

By performing automated functional analysis of RTL, PeriScope 

dramatically reduces SoC functional defects and cuts overall SoC

design and verification costs

Atrenta(R) Inc., the Predictive Analysis Company, introduced PeriScope(TM), an automated functional analysis solution that significantly reduces time and effort spent in the verification process for complex Systems on Chip (SoCs). Atrenta's PeriScope verifies and predicts back-end design problems during the front-end Register Transfer Level (RTL) development cycle. Expanding its proprietary market-leading predictive analysis technology into the functional analysis space, Atrenta's PeriScope helps engineers quickly determine if their RTL descriptions are functionally correct and fix any problem areas without the need for lengthy and repetitive simulation and synthesis runs. Atrenta's PeriScope product complements its existing SpyGlass(R) product, which is the industry standard technology for predictive structural analysis. As chip development costs at sub-180 nanometer geometries exceed tens of millions of dollars, designers must find alternative approaches to design that are economically viable. PeriScope's predictive functional analysis at RTL is a powerful approach that reduces the escalating time-to-market risk associated with complex SoCs.

Atrenta's PeriScope expands upon its leading predictive analysis technology, which detects structural problems in the design to identify functional problems in complex SoCs. PeriScope takes a predictive approach to verification by anticipating flaws in the design through functional analysis of front-end RTL. By identifying undetected, deep, hard-to-find functional problems such as clocking errors, unreachable code and tri-state bus conflicts early in the RTL design process, Atrenta reduces the need for lengthy and expensive simulation to catch functional design errors. PeriScope also brings the benefits of functional analysis to mainstream RTL designers doing VHDL, Verilog and mixed-language designs. Such an approach ensures more accurate, problem-free designs as a larger number of designers can be involved in the verification and debugging process early in the design cycle. It also allows chip-level verification engineers to check for clean RTL hand-off from system level designers.

"Our new PeriScope product is a direct result of feedback from our customers," stated Atrenta's VP of Marketing, John Rizzo. "While our proven SpyGlass Predictive Analyzer is great at finding a comprehensive set of design issues in RTL, our customers are also looking for automated functional analysis that pinpoints hard-to-find, complex problems in the design that jeopardize first-time silicon success. Current approaches are not easy to use and require verification experts to run them. PeriScope addresses these customer needs with a powerful automated solution that can deliver stellar results with very little user intervention. PeriScope can be deployed on a large scale in projects to enable each RTL designer to completely validate their RTL and improve verification productivity."

Functional Analysis Capabilities

Using an assertion-based verification engine under the hood for functional analysis, PeriScope adds advanced functional algorithms to the industry's most comprehensive structural Clock Domain Crossing (CDC) analysis capability. Since synchronizers are required on signals crossing clock domains, PeriScope automatically detects and reports missing or incorrect synchronizers. It also detects other complex clocking problems such as improper encoding of multi-bit CDC signals, re-convergent signals and hold-time issues for fast-to-slow clock crossings.

In addition to CDC analysis, PeriScope uses a combination of formal techniques and simulation to check for problems such as bus contention, control bus synchronization, un-initialized memory, and simultaneous set/reset. It provides functional verification of Finite State Machines (FSMs), including search for unreachable states, deadlock states, and inactive state transitions. It can also detect dead code and functionally validate tri-state busses and case statements.

Full-chip Capacity

PeriScope's CDC analysis can be run on the full chip. Unlike other products that can be used only at the block level, PeriScope tackles large gate count devices, thus saving time and increasing success by verifying the entire SoC at once.

Unified Environment

When used together, all of Atrenta's advanced analysis technologies for DFT, constraint analysis, and low power optimization can run within a common user interface and unified platform. This, for the first time, enables comprehensive and efficient SoC design and verification at the RT-level. By enabling RTL designers to predict and repair downstream design problems in the front-end design process, Atrenta significantly improves the economics of complex SoC design and prototyping. PeriScope solves one of the major challenges of functional analysis - once an issue is identified, it helps the designer find the root cause of the problem and fix it at RTL. PeriScope enables functional verification with little user intervention, opening up automatic functional analysis to RTL designers. As with Atrenta's SpyGlass predictive analyzer, design teams can add new custom checks to PeriScope to validate any kind of clock synchronization and other structures in RTL.

Support for OVL Assertions

Atrenta's PeriScope tool supports Accellera standard Open Verification Library (OVL) assertions including FIFO overflow and underflow, handshaking checks, and range checks. The PeriScope platform will also enable support for other popular assertion languages, such as PSL, which Atrenta plans to provide in the near future.

Availability

PeriScope is available on Solaris, HP-UX and Linux platforms. Pricing starts at $50,000 for a single time-based license.

About Atrenta

Atrenta delivers predictive analysis solutions to the world's leading electronics companies, including eight of the top ten semiconductor companies. Its pioneering and award-winning SpyGlass Predictive Analysis tools accelerate the design of SoCs, ASICs, and FPGAs by detecting complex chip design problems that are not easily identified with conventional verification methods. SpyGlass has been recognized through several distinguished awards, including EDN magazine's Top 100 products and "LSI Design of the Year" award by Japan's Semiconductor Industry News. Most recently, SpyGlass Constraints was named as an EDN Innovation Awards finalist for 2004. Atrenta was also chosen by Venture Reporter as one of the top 100 venture-backed companies, and named by AlwaysOn as one of the Top 100 private companies. Atrenta, with headquarters in San Jose, California, employs over 150 personnel worldwide. For further information, visit the Atrenta website at www.atrenta.com, email [e-mail], or call 408-453-3333.

Atrenta and SpyGlass are registered trademarks and PeriScope is a trademark of Atrenta Inc. All other trademarks belong to their respective owners.

(C) 2004 Atrenta Inc. All rights reserved.