Atrenta Gains Key Patents for Chip Design Analysis Technologies.Patents Awarded: -- Method for Determining Fault Coverage from RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; Description -- An Apparatus and Method for Handling of Multi-Level Circuit Design Data -- Method for Efficient Identification and Implementation of Clock Gating of Integrated Circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. -- Automatic Assertion Generation for Functional Validation of Integrated Circuits -- Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif. -- Strengthening its leadership position in early design analysis tools, Atrenta, today announced that it has been awarded five new patents by the U.S. Patent Office for significant chip design analysis technologies. These technologies drive Atrenta's SpyGlass(TM) tool-suite, an industry standard for design analysis. "These technologies augment Atrenta's solution, allowing our customers to perform accurate design analysis early in the design cycle. As a result, they are able to make their designs correct right from RTL phase, limit design costs, as well as, save design development time," said Bernard Murphy, Atrenta's chief technology officer. US patent 6,876,934, "Method for Determining Fault Coverage from RTL Description," allows users to accurately predict the ultimate test coverage by analyzing the RTL. US patent 6,993,733, "An Apparatus and Method for Handling of Multi-Level Circuit Design Data" enables the implementation of look-ahead design methodology by evaluating the high level RTL representation of a device. It quickly emulates the downstream implementation of the device, thus exposing potential implementation issues In the Business world, companies frequently set-up a connection between which they transfer data. When the connection is being set-up, it is referred to as implementation. When issues occur during this phase, they are known as implementation issues. early in the design or manufacturing cycle. US patent 7,076,748, "Method for Efficient Identification and Implementation of Clock Gating of Integrated Circuits," permits identification and implementation of clock gating in IC design to reduce dynamic power consumption. US patent 7,073,146, "Automatic Assertion Generation for Functional Validation of Integrated Circuits" provides a method for automatically detecting unstable clock-domain crossings in IC design and making a stability determination for a clock-domain crossing based on satisfaction of a stability function. US patent 7,152,216, "Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains" enables automatic insertion and verification of level shifter modules used in integrated circuits (ICs). About Atrenta Atrenta is the leading provider of broad-based design analysis solutions based on industry standard SpyGlass[TM] technology. Atrenta's design analysis tools deliver early design closure by eliminating downstream design problems and iterative discoveries. This leads to improved predictability and efficiency in SoC design phases including RTL design, IP reuse, Verification, logical and physical implementation. Atrenta has over 100 customers including the world's top 10 semiconductor companies. Think Early Design Closure, Think Atrenta! Visit www.atrenta.com to learn about our solutions for RTL analysis, RTL debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. , RTL synthesis, lint lint - A Unix C language processor which carries out more thorough checks on the code than is usual with C compilers. Lint is named after the bits of fluff it supposedly picks from programs. checker, low power, power estimation, power management, Design for Test (DFT DFT - discrete Fourier transform ), constraints management, Timing Exception Verification (TXV TXV Thermostatic Expansion Valve ), Clock Domain Crossings (CDC See Control Data, century date change and Back Orifice. CDC - Control Data Corporation ), formal verification, RTL Prototyping, design closure, Platform based Design (PBD PBD - Programmer Brain Damage ), IP reuse, system level design, synthesis, simulation etc. This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release. |
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