Atrenta's SpyGlass 3.0 Predictive Analysis Tool Detects Gate-level Problems in RTL Code; SpyGlass 3.0 Offers Industry's First Structural Analysis of RTL Code.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 14, 2002

Atrenta(TM) Inc. introduced SpyGlass(TM) 3.0, a predictive analysis tool that cuts integrated circuit (IC) design time by providing the industry's first structural analysis of RTL (register transfer level) code. With its built-in fast synthesis engine, SpyGlass 3.0 can detect very complex structural problems at RTL that otherwise only show up at the gate level. SpyGlass 3.0's new graphical user interface (GUI) correlates the RTL coding violations with schematics (automatically generated) to help designers get to the source of the problem and figure out the best way to debug their design.

By being able to predict at the RTL coding stage, problems that may surface later in the design cycle, SpyGlass helps eliminate time-consuming design iterations. The designs created are better optimized, reusable, and go through the design flow with minimal problems. An independent survey by Zeidman Consulting found that by using SpyGlass, designers can achieve a 15-20 percent reduction in the time to get new chips to market and a 10-15 percent reduction in design costs. This survey also found a 6X reduction in ramp-up time for knowledge capture and a 60 percent reduction in compliance checking for design reuse.

"Spyglass has been successfully employed as the standard qualification tool for Motorola's RTL reuse coding rules," noted Dr. Wolfgang Eisenmann, Engineering Manager, Architecture and Systems Platforms Group of Motorola's Semiconductor Products Sector. "By having the reuse rules automatically checked, SpyGlass saves us months of laborious manual checking on every new project. We are now further expanding the Spyglass application into other domains," Dr. Eisenmann added.

"SpyGlass 3.0 takes RTL analysis to a new level by being able to find the really hard structural problems for our customers, " stated Atrenta Chairman, CEO and President, Dr. Ajoy Bose. "By catching errors early, SpyGlass greatly reduces the number of design iterations and optimizes the RTL for downstream tools."

"At Agilent, we have defined a number of guidelines for RTL design and have found SpyGlass to be invaluable in helping designers meet these guidelines early in the design cycle," said Rob Aitken, R&D Section Manager at Agilent's Imaging Electronics Division. "We are able to program our guidelines in SpyGlass and have it check the RTL for compliance. Having a built-in synthesis engine allows us to check for problems that are difficult to detect with just RTL analysis and this avoids costly synthesis re-runs," Aitken added.

SpyGlass 3.0 uses predictive analysis to look at the structure of the design, finding down-stream problems that are not detectable by other methods including other rule checkers, simulators and formal verifiers. Atrenta has developed a unique technology that uses fast synthesis to create a gate-level representation so true structural analysis can be performed during the RTL design phase. SpyGlass 3.0's new GUI can display a schematic of the synthesized logic so designers can cross-probe between their RTL code and the schematic to get a good understanding of the problem and how it might best be fixed.

By evaluating the RTL code at a structural level, SpyGlass can find places where resources can be shared thereby optimizing area and power consumption. Additionally, SpyGlass can provide designers with an early rough gate count for their design. This lets designers do trade-off analysis early in the design cycle and experiment with the gate-count-costs involved in different design techniques.

SpyGlass 3.0 provides new customization analysis so the designer can add rules, enable and disable tests, and establish profiles that store a designer's selection of policies, rules and parameters. Designers can use either the PERL or C programming languages for this customization.

About Atrenta

Atrenta offers a new approach in accelerating the design of complex ASICs and SoCs through predictive analysis. Its SpyGlass is the first tool that performs detailed structural analysis on register-transfer-level Verilog and VHDL code in order to check for complex problems, which include coding styles, RTL-handoff, design re-use, clock/reset requirements, and much more. Its breakthrough and innovative "look-ahead" capability incorporates a fast-synthesis engine, cycle-based simulation, and testability technologies. Atrenta has over forty customers, including Agere, Agilent, Apple, ARM, Canon, Compaq, Fujitsu, Hitachi, LSI Logic, Motorola, National Semiconductor, NCR, Nortel and Olympus, who are using SpyGlass to achieve shorter overall design cycles, increased design productivity and lower costs.

Atrenta is headquartered in San Jose, California, with European headquarters in Swindon, England, a research and development center in India, and a sales and support distributor in Japan. For further information, visit the Atrenta website at www.atrenta.com or call 1-866 ATRENTA.

Note to Editors: Atrenta and SpyGlass are trademarks of Atrenta Inc.