Atmel and Synplicity Provide Synthesis Solution for AT40K FreeRAM FPGAs; Atmel/Synplicity Solution Exploits Atmel Macro Generator Capability.SAN JOSE, Calif.--(BUSINESS WIRE)--April 28, 1999-- Atmel Corporation, (Nasdaq:ATML ATML Automatic Test Markup Language ATML Automated Test Markup Language ) a leading supplier of programmable logic solutions and Synplicity, Inc. today announced support between Atmel's AT40K FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. version 6.0 development software and the popular Synplicity Synplify(R) logic synthesis tool. Atmel's patented AT40K FPGA architecture supports high performance DSP-based designs by using a combination of its DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive optimized core cell and on-chip diagonal connections. The AT40K FPGAs features are exploited by the Synplicity's Synplify software through technology mapping of HDL-based designs directly into the AT40K core cell structure. In addition, the Synplicity Synplify software identifies logic structures and passes system block requirements to Atmel's unique macro generator software tools, exploiting the full capabilities AT40K architecture. "Synplicity Synplify logic synthesis tool does a great job at recognizing the complex IP blocks in HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. code that allow the real architectural benefits of Atmel's AT40K FPGAs to be exploited," said Atmel's FPGA product marketing manager, Martin Mason. "Not only are multiplier structures mapped efficiently, but other large blocks like SRAMs are also identified. The Synplicity Synplify tool takes advantage of the AT40K architecture and compiles HDL code at blistering speeds, we have been very pleased with the results." About Atmel FPGA Designer 6.0 Atmel's FPGA Designer 6.0 will be provided at no charge to qualified Synplicity users. This will allow existing users to target designs to Atmel' s AT40K, Xilinx pin compatible FPGAs with FreeRAM(TM). FOPGA Designer 6.0 is available free of charge to other qualified designers for a limited time via Atmel at: www.atmel.com/fpga_software.html. The FPGA Designer 6.0 incorporates a suite of industry-standard design tools including HDL Planner, netlist import, technology mapping, mult i-chip partitioning, automatic logic and RAM compilers, timing-driven automatic placement and routing, interactive timing analysis and bitstream generation & utilities. AT40K FPGAs The AT40K is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10ns programmable synchronous/asynchronous, dual port/single port SRAM See static RAM. SRAM - static random-access memory , 8 global clocks, Cache Logic(R) ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 150,000 usable gates. I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output counts range from 128 to 384 in industry-standard packages ranging from 84-pin PLCC (Plastic Leaded Chip Carrier) A plastic, square, surface mount chip package that contains leads on all four sides. The leads (pins) extend down and back under and into tiny indentations in the housing. See chip package. to 475-pin PGA (1) (Professional Graphics Adapter) An early IBM PC display standard for 3D processing with 640x480x256 resolution. It was not widely used. (2) (Programmable Gate Array) See gate array and FPGA. , and support 3V and 5V designs. Synplify First introduced in 1995, Synplicity's Synplify synthesis tool represents a new breed of synthesis tools de signed independent of existing academic or commercial code and features the Company's innovative B.E.S.T.(TM) algorithms. The tool accepts industry-standard Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. descriptions and produces optimized implementations for programmable devices from many leading vendors. The recent release of Synplify 5.0 contains a unique multi-level timing constraints management system, giving designers, for the first time, the most accurate automated solution combined with the most robust user-controlled features, providing designers flexibility in the way they use their synthesis tool. Designed to deliver the highest quality of results, Synplify is also extremely fast and easy-to-use. It includes a built-in language-sensitive editor and optional graphical (block diagram) analysis tool that gives direct feedback for fast design debug. Founded in 1994, Synplicity, Inc., delivers the benefits of logic synthesis and embedded synthesis technologies to programmable logic designers by developing fast, easy, affordable Electronic Design Automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools with extremely high quality of results. Synplicity products support industry-standard design languages (VHDL and Verilog), run on popular platforms (Windows '95, Windows NT and UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). ), and support leading PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. manufacturers. The specific features, functionality and release timing of any new products or new versions of current products remains at the sole discretion of Synplicity, Inc., and no warranty is made as to when or if specific features, functionality or releases may occur. The Company is located at 610 Caribbean Drive, Sunnyvale, CA 94089. Telephone: 408/548-6000; Fax: 408/548-0050; e-mail: info@synplicity.com Founded in 1984, Atmel Corporation is headquartered in San Jose, Calif. with principal manufacturing facilities in Colorado Springs, Colo., Nantes and Rousset, France and Heilbronn, Germany. Atmel designs, manufactures and markets on a worldwide basis advanced logic, mixed-signal, nonvolatile memory, and RF semiconductors. Atmel is also a leading provider of system level integration semiconductor solutions using advanced CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. , BiCMOS, BiPolar and SiGe process technologies. Atmel product and financial information are available from its Fax-on-Demand service. In North America call 800/292-8635 or Internationally, call 408/441-0732. Requests may be made via e-mail to literature@atmel.com or by visiting Atmel's web site at www.atmel.com. Note to Editors: Atmel, the Atmel logo and combinations thereof are trademarks of Atmel Corporation. Additional terms and product names in this document may be trademarks of others. |
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