Atmel Ships SystemDesigner Programmable System-on-Chip Design Tools; Integrated Tool Set With Co-Verification Enables Desktop-Based System-on-Chip Design.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Aug. 1, 2000 Atmel Corp. (Nasdaq:ATML ATML Automatic Test Markup Language ATML Automated Test Markup Language ) today announced the immediate availability of its Field Programmable System Level Integration Circuit (FPSLIC FPSLIC Field Programmable System Level Integrated Circuit (TM)) design tool -- SystemDesigner(TM). SystemDesigner is the industry's first integrated tool suite with co-verification available for creating and implementing programmable system-on-chip (SOC) designs. SystemDesigner provides everything necessary to implement SOC designs on the desktop -- including Atmel's advanced FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. timing driven place & route and AVR (Automatic Voltage Regulation) See voltage regulator. microcontroller development and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. tools; Exemplar Synthesis, Model Technology hardware simulator and co-verification powered by Mentor's Co-verification tools. Co-verification is an important design tool that enables both the hardware simulator for the FPGA HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. code to interact directly with the instruction set simulator An Instruction Set Simulator (ISS) is a simulation model, usually, but by no means always, coded in a high-level language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's of the processor. This enables the hardware and software elements of a system to be designed and verified using a `virtual prototype' early in the design process -- eliminating the need for hardware emulation Hardware emulation is the process of imitating the behavior of one or more pieces of hardware (typically a system under design) with another piece of hardware, typically a special purpose emulation system. The goal is normally debugging of the system being designed. and multiple printed circuit board redesigns. The Co-verification tools are the first offered for programmable logic design -- significantly reducing design time, risk and overall cost of system development. "Atmel's FPSLIC architecture integrates an embedded processor, FPGA and other Intellectual Property cores on a single slice of silicon," stated Martin Mason, Atmel's Programmable SLI (Scalable Link Interface) A multi-GPU interface from NVIDIA for connecting two or four NVIDIA display adapters together for faster graphics rendering on one monitor or two monitors. Marketing Manager. "FPSLIC combines the flexibility of programmable logic with system-level integration while bringing advanced processor technology to the broad marketplace." "FPSLIC differs from high density FPGAs by implementing the processor, memory and peripherals as hardwired fixed logic (ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. gates), while the FPGA portion enables customization and provides the flexibility benefits associated with programmable logic. With FPSLIC and SystemDesigner developers can focus on defining the system functionality, rather than worrying about implementation issues such as whether the processor will fit in the FPGA and run at the correct speed. This results in significantly faster time-to-market, reduced power consumption, lower device cost, higher performance designs and lower design risk," Mason concluded. "FPSLIC is a platform architecture that supports the implementation of various combinations of 8-bit through 64-bit and higher processors along with different size FPGA cores, program and data memory, peripherals and other fixed and custom logic," said Joel Rosenberg, Product Line Director for Programmable System Level Integration. "If the system design requires additional custom logic, those functions can be programmed into the FPGA and, if required, mapped directly into the address space of the embedded processor." "SystemDesigner is a comprehensive design tool that can support virtually any industry standard processor core available today, as well as industry standard synthesis and simulation tools. This powerful platform enables Atmel to leverage its ASIC, FPGA, Memory and Processor and associated design tool capabilities to bring a family of devices that offer the programmable benefits of FPGA to the System-on-chip marketplace," Rosenberg continued. "The limitations of custom system-on-chip ASIC design today include design tool costs, mask charges, licensing fees and other non-recurring engineering charges that can bring the total development costs for a single chip to over $1 Million. The high costs, risk and volume production requirements associated with custom SOC design put this capability out of reach for most applications today," Rosenberg concluded. About AT94 Field Programmable System Level Integration Circuits (FPSLIC) The in-system programmable AT94K FPSLIC family integrates all the major building blocks required for system level design -- up to 40,000 gates of Atmel's AT40K (Field Programmable Gate Array See FPGA. ) with FreeRAM(TM), 30+ MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. AVR(R) RISC processor, 32 Kbytes of program memory, 4K of data memory and frequently used on chip peripherals such as UARTs, timer/counters, an industry standard 2-wire serial bus and a hardware multiplier. Additional peripherals can be created in the FPGA and mapped directly in the address space of the microcontroller. The entire device is SRAM-based, allowing both the instruction set for the microcontroller and the hardware code for the FPGA to be reconfigured in-system, any number of times, either during development, production, or remotely at the end-customer sight. The benefits of this solution can provide up to 70% board area reduction, 50% lower power consumption, 50% performance improvement, and significantly reduced development cycles over discrete and other programmable solutions. Market research estimates the market for such devices could exceed $40 billion in the next 10 years, potentially dwarfing the existing $5B programmable logic market. About Co-Verification Co-verification enables designers to simulate software and hardware concurrently during product development by using state of the art co-verification tools developed by Mentor Graphics. SystemDesigner's co-verification design methodology fully synchronizes FPGA hardware and RISC processor software execution, and provides source and assembly-level software debugging with full visibility into the FPSLIC's memory, registers and hardware logic. Co-verification has been documented to significantly reduce product development cycles by allowing a virtual prototype of the complete FPSLIC system to be verified early in the design process. Pricing and Availability The SystemDesigner(TM) EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools suite works on Windows(R) 95/98/200/NT platforms, is available now, and is priced at an annual subscription price of $995. The AT94K40 FPSLIC device which includes Atmel's 8-bit RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. AVR microcontroller, 40K gate embedded AT40K FPGA, and 36 Kbytes SRAM See static RAM. SRAM - static random-access memory is shipping now and is priced from $50. Additional AT94K family members will be available in Q4, 2000. Prices in 2001 for AT94K products will start below $7 in production volumes of 250K units. About Atmel Founded in 1984, Atmel Corp. is headquartered in San Jose, with manufacturing facilities in Colorado Springs, Colo.; Irving, Texas; Grenoble, Nantes and Rousset France; and Heilbronn, Germany. Atmel designs, manufactures and markets on a worldwide basis advanced logic, mixed-signal, non-volatile memory, and RF semiconductors. Atmel is also a leading provider of system level integration semiconductor solutions using advanced CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. , BiCMOS, Bipolar and SiGe process technologies. Atmel product and financial information are available from its Fax-on-Demand service. In North America call 800/292-8635 or Internationally, call 408/441-0732. Requests may be made via e-mail to literature@atmel.com or by visiting Atmel's web site at www.atmel.com. Note to Editors: Atmel, the Atmel logo and combinations thereof and others contained herein, are trademarks of Atmel Corp. Terms and product names in this document may be the trademarks of others. |
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