Atmel Introduces a New 0.35 Micron CMOS Radiation Hard ASIC Library Dedicated to Space Applications.

Business Editors/High-Tech Writers

NANTES, France--(BUSINESS WIRE)--Oct. 30, 2001

Atmel(R) Corporation (Nasdaq:ATML) announced today the release of the MH1RT series, a set of ASIC Sea of Gates 0.35 micron libraries which provide the Aerospace industry with a level of integration of up to 1.6 million usable gates, and a capability of radiation hardness up to 300 K Rads.

Developed during a three-year partnership program started late in 2000 between the Centre National d'Etudes Spatiales (CNES), the European Space Agency (ESA) and Atmel, the MH1RT libraries encompass all the specific digital functions and buffers necessary for space designs, such as LVDS(1) and PCI(2) buffers, SEU(3) immune DFFs(4), and cold sparing capability buffers. All ASICs can be designed with either 3.3 V, 3 V or 2.5 V libraries, and the buffers are capable of interfacing either with 3 V or 5 V logic.

Following its partnership strategy with leading customers, Atmel has successfully prototyped multiple radiation hard MH1RT ASICs, representative of the maximum gate count complexity, including multiple complex and compiled memory blocks. These new ASICs libraries are available under the QML V 5962-01B01 Standard Military Drawing, the highest complexity currently listed by Defense Supply Center Columbus (DSCC).

Dominique de Saint Roman, marketing manager for Aerospace ASIC at Atmel, said "Our objective is to offer ever increasing gate integration capability, combined with the cells, buffers and IPs necessary to open the way towards the future generation of Radiation-Tolerant System on Chip solutions."

The available set of matrix and package combinations can address pin count complexity up to 472 pins, using a hermetic ceramic BGA type (the Ceramic Land Grid Array combined with a Solder Column Interposer).

Design kits are available for Cadence/Verilog, Mentor and Synopsys platforms. They include all the libraries for simulation and synthesis. Customer support is provided by dedicated design centers in Europe (London, Milan, Munich, Nantes and Paris) and the U.S. (San Jose, Calif.).

The development of next generation of libraries, based on standard cells characterized on a 0.25 micron CMOS hardened technology, is ongoing and should be released by next year. It will allow ASIC designs with complexity above 5 million gates.

(1) LVDS: Low Voltage Differential Swing

(2) PCI: Peripheral Component Interconnect 

(3) SEU: Single Event Upset

(4) DFF: Data Flip Flop

About Atmel

Founded in 1984, Atmel Corporation is headquartered in San Jose, Calif. with manufacturing facilities in North America and Europe. Atmel designs, manufactures and markets worldwide, advanced logic, mixed-signal, nonvolatile memory and RF semiconductors. Atmel is also a leading provider of system-level integration semiconductor solutions using CMOS, BiCMOS, bipolar SiGe, and high-voltage BCDMOS process technologies.

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Information Atmel product information may be retrieved at http://www.atmel-wm.com/spaceasic.htm